Question 1

Q.1. Define Entity.

Accepted Answer

An entity in VHDL is the basic design unit that defines the external interface (input/output ports and generic parameters) of a digital circuit, without describing its internal implementation.

Question 2

Q.2. What is behavioural model?

Accepted Answer

A behavioural model describes a circuit's functionality through an algorithmic description of its input-output relationship (using process statements and sequential code), rather than describing its internal structural composition.

Question 3

Q.3. What is resolution function?

Accepted Answer

A resolution function in VHDL is a function that determines the single resultant value of a signal when multiple concurrent drivers attempt to assign different values to that same signal simultaneously.

Question 4

Q.4. What are the various sources of power dissipation in CMOS circuits?

Accepted Answer

The various sources of power dissipation in CMOS circuits are dynamic (switching) power, short-circuit power, and static (leakage) power.

Question 5

Q.5. What are test benches.

Accepted Answer

Test benches are VHDL simulation-only constructs that generate stimulus signals and apply them to a design under test, used purely for verification and never synthesized into actual hardware.

Question 6

Q.6. Why is NAND gate preferred over NOR gate for fabrication.

Accepted Answer

NAND gates are preferred over NOR gates for CMOS fabrication because electron mobility exceeds hole mobility, making NAND's series NMOS transistors more area/speed efficient than NOR's series PMOS transistors, which would otherwise need to be oversized to compensate for lower hole mobility.

Question 7

Q.7. Write the characteristics of CMOS logic families.

Accepted Answer

CMOS logic families are characterized by very low static power dissipation, full rail-to-rail output voltage swing, high noise margins, and a naturally complementary pull-up/pull-down transistor network structure.

Question 8

Q.8. In a 2-input CMOS logic gate, one input is left floating i.e., connected…

Accepted Answer

A floating CMOS input (connected neither to ground nor a driven signal) has an undefined, indeterminate logic state that can drift due to leakage currents, potentially causing both the PMOS and NMOS transistors to partially conduct simultaneously, resulting in excess static current flow.

Question 9

Q.9. Define Accumulation Phenomenon in MOS structure.

Accepted Answer

Accumulation is the MOS structure condition in which a negative gate voltage (for an n-type substrate/NMOS body context) attracts majority carriers toward the oxide-semiconductor interface, increasing majority carrier concentration near the surface above the bulk equilibrium value.

Question 10

Q.10. What is Body Effect?

Accepted Answer

Body effect is the increase in a MOSFET's threshold voltage magnitude that occurs when a non-zero (reverse-biased) source-to-body voltage is present, due to the additional depletion charge required beneath the gate.

Question 11

Q.1. The CMOS circuit shown implements a compound AND-OR-INVERT/OR-AND-INVERT…

Accepted Answer

Analyzing the CMOS circuit's pull-up (PMOS: C in series, then A parallel B, then D in series) and dual pull-down (NMOS: A series B, in parallel with C, in parallel with D) networks using standard series-equals-AND-conduction/parallel-equals-OR-conduction duality rules shows the circuit implements Y = NOT(AB + C + D), a 4-input AND-OR-INVERT (AOI) gate.

Question 12

Q.2. A digital CMOS IC operating at 10MHz clock frequency consumes 100mW powe…

Accepted Answer

For the given digital CMOS IC (100mW at 10MHz, 140mW at 15MHz), treating total power as static power plus a frequency-dependent dynamic power term (P=Pstatic+k*f), solving the two simultaneous equations gives a dynamic power coefficient k=8 mW/MHz and static power consumption Pstatic=20mW.

Question 13

Q.3. Design a 3-Input NAND gate using CMOS such that its pull up to pull down…

Accepted Answer

A 3-input CMOS NAND gate is designed with a pull-up-to-pull-down equivalent resistance ratio of 3:1 by appropriately sizing the parallel PMOS transistors (each sized for unit strength) and the series NMOS transistors (each sized wider, by a factor of 3 divided by the mobility-ratio-adjusted requirement, to compensate for the series resistance stacking of three NMOS transistors while achieving the specified overall 3:1 ratio).

Question 14

Q.4. Draw stick diagram layout for:

Accepted Answer

Stick diagrams provide a simplified, color-coded topological layout representation of a CMOS circuit showing the relative placement and connectivity of diffusion, polysilicon, and metal layers without exact dimensions; a 2-input NAND gate's stick diagram shows two series NMOS diffusion strips crossed by two polysilicon gate lines with parallel PMOS diffusion above, while an Ex-OR gate's stick diagram is typically realized using a more complex multi-transistor arrangement or a transmission-gate-based topology given its non-trivial series-parallel switching function.

Question 15

Q.5. What is C-squared MOS logic? Draw any logic circuit using it. What are a…

Accepted Answer

C2MOS (Clocked CMOS) logic is a dynamic logic family in which each gate stage is controlled by a clock signal that alternately isolates the stage during one clock phase and evaluates/passes data during the other phase, providing race-free pipelining without the charge-sharing vulnerabilities of simple dynamic (domino) logic, and with reduced clock loading compared to fully static master-slave latch-based pipelining.

Question 16

Q.6. Write the difference between custom design and FPGA in respect of design…

Accepted Answer

Custom (full-custom) IC design requires substantially longer design time and higher non-recurring engineering (NRE) cost than FPGA-based design, but achieves superior area, speed, and per-unit power/cost efficiency at high production volumes, whereas FPGA design offers much faster time-to-market and lower upfront cost, at the expense of higher per-unit cost and generally lower performance, making FPGAs preferable for prototyping, low-to-medium volume production, and applications requiring post-deployment reconfigurability.

Question 17

Q.7. Explain NORA CMOS logic circuit in details.

Accepted Answer

NORA (NO-RAce) CMOS logic is a race-free dynamic logic style built from alternating cascaded blocks of C2MOS and dynamic (domino-like) logic stages, using two alternating clock phases so that a signal transition originating in one stage cannot race ahead and corrupt an evaluation still in progress in the immediately following stage, combining the compactness of dynamic logic with reliable pipelined operation across multiple cascaded logic stages.

Question 18

Q.1. Draw following and explain their working.

Accepted Answer

The SRAM cell (6 transistors: a cross-coupled inverter pair plus two access transistors) provides fast, static (non-refreshing) bistable data storage; the DRAM cell (1 transistor plus 1 capacitor) provides much denser but volatile storage requiring periodic refresh due to capacitor leakage; domino logic implementing y=NOT(AB+C) uses a precharge-evaluate dynamic NMOS pull-down network followed by a static inverter buffer to restore proper non-inverting domino output behavior; NP (Zipper) domino logic alternates N-tree and P-tree dynamic stages (similar in principle to NORA logic) to allow direct, race-free cascading of dynamic gates without an inverter buffer between every stage.

Question 19

Q.2. Using the example of full adder, Compare and contrast the data flow, beh…

Accepted Answer

Comparing dataflow, behavioural, and structural VHDL modeling styles using a full adder example: dataflow style uses concurrent Boolean signal assignments directly expressing Sum and Cout equations; behavioural style uses a process block with sequential/algorithmic statements (or a truth-table-based case statement) to describe the same function; structural style instantiates and interconnects lower-level component gates (or half-adder sub-modules) to build up the full adder, each style offering different trade-offs in code readability, simulation/synthesis efficiency, hierarchy support, and design reusability.

Question 20

Q.3. Draw the CMOS inverter and discuss its DC characteristics. Write the con…

Accepted Answer

The CMOS inverter's DC (voltage transfer) characteristic exhibits five distinct operating regions as input voltage sweeps from 0 to VDD, defined by the specific combination of triode/saturation/cutoff conditions for the NMOS and PMOS transistors at each input voltage level, with the sharp transition region (where both transistors are in saturation) giving the inverter its high voltage gain and good noise margin characteristics.

Question 21

Q.4. What type of language is VHDL? Explain advantages and limitation of VHDL…

Accepted Answer

VHDL (VHSIC Hardware Description Language) is a hardware description language used for both modeling/simulation and synthesis of digital circuits, based on the Ada programming language, offering advantages including technology independence, support for top-down hierarchical design, pre-fabrication simulation verification, and standardization under IEEE 1076, while its limitations include a comparatively steep learning curve, restrictive synthesizable-subset constraints compared to its full simulation capability, and verbose syntax compared to some competing hardware description languages.

Question 22

Q.5. Draw the following Circuits

Accepted Answer

The three requested circuits are: y=A.NOT(B).C implemented as a standard 3-input static CMOS AND-type gate (series NMOS pull-down for A, inverted-B, and C, with the dual parallel PMOS pull-up network); a 1-bit CMOS memory cell implemented as a cross-coupled inverter latch with an access transistor; and y=A XOR B implemented using two transmission gates controlled by A and its complement, selecting between B and NOT(B) at the output.

CMOS Design