Q7CMOS Design

NORA CMOS Logic

NORA (NO-RAce) CMOS logic is a dynamic CMOS logic design style specifically developed to eliminate the race conditions that can occur when multiple dynamic logic gates are directly cascaded together in a pipeline, by structuring the overall pipeline as an alternating sequence of two distinct block types - N-blocks and P-blocks - each operating during opposite phases of a two-phase (or single-phase-with-complement) clock, ensuring that signal transitions can only propagate correctly, one stage per active clock phase, without ever racing ahead into a stage that has not yet finished evaluating.

N-blocks are dynamic logic gates using an NMOS pull-down evaluation network (similar in structure to conventional domino logic), precharged (via a clocked PMOS transistor) during one clock phase and evaluated (via a clocked NMOS transistor enabling the pull-down network) during the opposite clock phase. P-blocks are the complementary dynamic structure, using a PMOS pull-up evaluation network, precharged low during one clock phase and evaluated (pulling the output high through the PMOS network, when the appropriate input conditions are met) during the opposite clock phase relative to the N-blocks.

Race-free operation principle: by alternating N-blocks and P-blocks along the pipeline, with N-blocks precharging while P-blocks evaluate (and vice versa on the following clock phase), each stage's output remains valid and stable throughout the entire clock phase during which the next stage needs to evaluate using that output as its input, and no stage can begin corrupting/precharging its own output at the same moment the following stage is still relying on reading a stable, previously-evaluated value from it - this alternating N-block/P-block structure, combined with correctly-phased two-phase (or complementary single-phase) clocking, is what gives NORA logic its race-free (NO-RAce) property when cascading many dynamic logic stages in a pipelined datapath, addressing the fundamental race-condition vulnerability of naively cascading multiple simple domino logic stages directly together within a single clock phase (where a fast-evaluating early stage could inadvertently propagate a transition into a later stage before that later stage's own precharge has properly completed, corrupting the pipeline's correct operation).

Relationship to C2MOS and domino logic: NORA logic can be understood as a generalization and formalization of the earlier C2MOS pipelining technique (discussed in the corresponding earlier answer) combined with the area/speed efficiency advantages of domino-style dynamic evaluation logic - where a pure C2MOS pipeline typically uses simple clocked static-like inverting/buffering stages, NORA logic extends this same race-free alternating-clock-phase principle to full dynamic (domino-style) evaluation logic gates capable of implementing more complex Boolean functions directly within each pipeline stage, combining the compact, fast switching characteristics of dynamic logic with the reliable, race-free pipelined cascading behavior that simple domino logic alone cannot guarantee when multiple stages are cascaded without additional structural precautions. NORA logic found significant use in high-performance microprocessor datapath design during the era when dynamic logic techniques were extensively employed to maximize clock frequency for a given fabrication process, though it requires careful attention to clock distribution (minimizing clock skew between the alternating phases) and is generally more complex to design and verify correctly than straightforward fully-static CMOS logic, a trade-off that has led modern high-performance digital design to rely on dynamic logic techniques such as NORA more selectively, in specific speed-critical circuit blocks, rather than throughout an entire chip design.