Q4CMOS Design
Question
Q.4. Draw stick diagram layout for:
- (i) 2-Input CMOS NAND gate.
- (ii) Ex-OR gate.
Answer
Stick diagrams provide a simplified, color-coded topological layout representation of a CMOS circuit showing the relative placement and connectivity of diffusion, polysilicon, and metal layers without exact dimensions; a 2-input NAND gate's stick diagram shows two series NMOS diffusion strips crossed by two polysilicon gate lines with parallel PMOS diffusion above, while an Ex-OR gate's stick diagram is typically realized using a more complex multi-transistor arrangement or a transmission-gate-based topology given its non-trivial series-parallel switching function.
Stick Diagram Conventions
A stick diagram is a simplified graphical layout representation used in VLSI physical design to show the relative topological arrangement and interconnection of a circuit's diffusion regions, polysilicon gates, and metal interconnect layers, without representing exact physical dimensions, spacing rules, or design-rule details - stick diagrams serve as an intermediate planning step between a circuit's transistor-level schematic and its final, fully dimensioned physical mask layout, using standard color/line-style conventions: green (or a solid line) for n-diffusion, red (or a dashed line) for p-diffusion, red/orange (a distinct color) for polysilicon (gate material), and blue/other colors for metal interconnect layers, with small circles typically marking contact/via connections between different layers.
(i) Stick Diagram for 2-Input CMOS NAND Gate
The stick diagram for a 2-input NAND gate shows two horizontal diffusion strips: an upper p-diffusion strip connected to the VDD rail (hosting the two parallel PMOS transistors) and a lower n-diffusion strip connected to the GND rail (hosting the two series NMOS transistors), with two vertical polysilicon lines (one for input A, one for input B) crossing both diffusion strips at the points where the actual transistor gates are formed - the p-diffusion strip is arranged so both PMOS transistors' source/drain regions connect directly in parallel between VDD and the output node (both PMOS drains tied together to a common output metal contact), while the n-diffusion strip is arranged as a single continuous strip broken only by the two polysilicon gate crossings, naturally forming the required series NMOS connection (source of one NMOS transistor directly forms the drain of the adjacent one, with no separate metal jumper needed for this internal series node), with the final common output node (where both the parallel PMOS drains and the series NMOS chain's outer end meet) connected via a metal contact to form the gate's output Y.
(ii) Stick Diagram for Ex-OR Gate
An Exclusive-OR (XOR) gate, implementing Y=A XOR B=A.NOT(B)+NOT(A).B, does not reduce to a simple single series/parallel NMOS-PMOS dual network in the same straightforward way as a NAND or NOR gate, since its Boolean expression is not expressible as a pure AND-OR (or OR-AND) structure of the uncomplemented and complemented literals alone without requiring both true and complemented versions of both inputs A and B to be available - a static CMOS realization of XOR therefore typically requires either: (a) first generating the complements NOT(A) and NOT(B) using two separate inverter stick-diagram cells (each a simple single PMOS/single NMOS stack), then combining A, NOT(A), B, NOT(B) through a more complex compound AOI/OAI pull-up/pull-down network requiring 8 or more transistors total, laid out as an extended version of the compound-gate stick diagram technique described in the corresponding Part B Q1 circuit-analysis answer elsewhere in this paper, with two separate series-pairs (A-series-NOT(B), and NOT(A)-series-B) connected in parallel in the pull-down network (and the complementary dual arrangement in the pull-up network); or (b) a more compact transmission-gate-based XOR implementation, using only 6 transistors (two inverters plus two transmission gates), which is generally preferred in modern CMOS layout practice for its reduced area and improved switching characteristics, and whose stick diagram would show two small inverter cells (for generating NOT(A) or NOT(B)) placed adjacent to a pair of transmission-gate cells (each transmission gate itself consisting of one NMOS and one PMOS transistor with their source/drain terminals tied together and gates driven by complementary control signals), with the specific layout and routing of the transmission-gate control signals (A, NOT(A) or B, NOT(B), depending on the chosen transmission-gate XOR topology) requiring careful attention to minimize the wiring/routing complexity in the final stick diagram.