Q5CMOS Design

C-Squared MOS (Clocked CMOS) Logic

C2MOS (Clocked CMOS) logic is a dynamic CMOS logic family in which each logic gate stage incorporates additional clock-controlled transistors (in series with the standard pull-up PMOS and pull-down NMOS networks) that alternately disconnect the gate from the supply rails during one clock phase and connect it to actively evaluate and drive its output during the other clock phase, providing a race-free method of cascading multiple pipelined logic stages using a single clock signal (and its complement) rather than requiring the more transistor-intensive master-slave flip-flop-based latching typically needed in fully static pipelined logic.

Basic C2MOS inverter structure: a C2MOS inverter stage consists of four series-connected transistors between VDD and ground: a PMOS gated by CLK-bar (the clock's complement), a PMOS gated by the input signal, an NMOS gated by the input signal, and an NMOS gated by CLK, stacked in that order - when CLK=1 (and CLK-bar=0), the top PMOS (gated by CLK-bar=0) and the bottom NMOS (gated by CLK=1) are both turned on, enabling the stage to actively evaluate its input and drive its output normally, exactly like a conventional static inverter; when CLK=0 (and CLK-bar=1), both the top PMOS (gated by CLK-bar=1, off) and the bottom NMOS (gated by CLK=0, off) are turned off, completely disconnecting the inverter's internal pull-up and pull-down networks from both supply rails, causing the output node to enter a high-impedance state and retain (hold) its previously-driven output value on its own output node capacitance, exactly as in simple dynamic (precharge-based) logic, but without requiring an explicit precharge transistor.

Additional Advantages of C2MOS Logic

• Race-free pipelining: by cascading successive C2MOS stages with alternating clock phases (one stage active during CLK-high, the next during CLK-low), data propagates through the pipeline in a controlled, race-free manner, since each stage is guaranteed to be in its high-impedance (isolated) hold state whenever the adjacent stage feeding it is actively evaluating, preventing the kind of race condition that can occur if data propagates too quickly through multiple cascaded simple dynamic (domino) logic stages within a single clock phase.
• No charge-sharing vulnerability (compared to simple dynamic logic): unlike a simple precharge-evaluate dynamic gate (domino logic), whose precharged output node capacitance can be corrupted by unwanted charge redistribution ('charge sharing') with internal parasitic node capacitances within the pull-down network during evaluation, a C2MOS stage's structure (built from a standard static-CMOS-like series PMOS/NMOS pair, merely gated additionally by the clock) does not suffer from this same internal charge-sharing vulnerability in the same way, since it is fundamentally an inverting/buffering stage rather than a complex multi-transistor evaluation network with multiple internal nodes.
• Reduced clock loading compared to master-slave static latches: a fully static master-slave flip-flop-based pipeline register requires a substantially larger number of transistors (and correspondingly larger clock-driver loading) per pipeline stage compared to the comparatively compact C2MOS latch/register structure, making C2MOS an attractive lower-power, lower-area alternative specifically for high-throughput pipelined datapath design.
• Inherent output holding (memory) capability: the high-impedance hold state during the inactive clock phase gives each C2MOS stage an inherent latching/memory capability without requiring any additional dedicated latch transistors, directly integrating the pipeline register function into the logic gate itself rather than requiring separate logic and latch circuit stages.

These combined advantages made C2MOS logic historically popular (notably used in early microprocessor and calculator chip designs) for implementing high-speed, area-efficient pipelined digital datapaths, though it requires careful attention to clock skew and clock-signal integrity (since incorrect relative timing between the true and complement clock signals driving successive stages can reintroduce the very race conditions the technique is designed to avoid) and has since been supplemented by further-refined dynamic logic families (such as True Single-Phase Clocking, TSPC, which achieves similar race-free pipelining benefits using only a single clock phase rather than requiring both true and complement clock signals to be routed throughout the chip).