Q3CMOS Design

CMOS Inverter Circuit

The CMOS inverter consists of a single PMOS transistor connecting the output node to VDD and a single NMOS transistor connecting the output node to ground, with both transistors' gates tied together to the common input Vin - as Vin sweeps from 0V to VDD, the NMOS transistor (which requires Vgs>Vtn to conduct) transitions from cutoff (off) through saturation to the triode region, while the PMOS transistor (which requires Vsg>|Vtp| to conduct, i.e., Vin<VDD-|Vtp|) transitions in the opposite direction, from triode through saturation to cutoff.

Voltage Transfer Characteristic (VTC) - Five Regions

• Region A (0 <= Vin < Vtn): the NMOS is in cutoff (Vgs=Vin<Vtn, off), while the PMOS is in the triode (linear) region (since Vsg=VDD-Vin is large, well above |Vtp|). With no NMOS pull-down current path, the PMOS pulls the output fully to Vout=VDD, and the inverter output is in its high logic state.
• Region B (Vtn <= Vin < Vinv, where Vinv is the switching threshold near VDD/2): the NMOS turns on and enters saturation (since Vds=Vout is still large, close to VDD, exceeding Vgs-Vtn), while the PMOS remains in the triode region - a small NMOS current begins to flow, pulling the output down slightly from VDD, but the output remains close to VDD in this region since the PMOS in the triode region presents relatively low resistance while the NMOS in saturation limits current flow.
• Region C (Vin near the switching threshold Vinv, where Vin approximately VDD/2 for a symmetrically-sized inverter): both the NMOS and PMOS transistors are simultaneously in saturation - this narrow but critical region is where the inverter's output undergoes its sharp, high-gain transition from VDD toward 0V (or vice versa), since with both transistors in the current-source-like saturation region, a very small change in Vin produces a very large change in Vout (very high small-signal voltage gain, dV_out/dV_in), giving the inverter its characteristic steep transfer curve and, correspondingly, good noise margins in the adjacent regions.
• Region D (Vinv < Vin <= VDD-|Vtp|): the PMOS transitions into saturation (since Vsd=VDD-Vout is now large, as Vout has fallen), while the NMOS enters the triode region (since Vds=Vout is now small) - the NMOS in the triode region now presents low resistance while the PMOS in saturation limits current, and the output continues falling toward 0V.
• Region E (VDD-|Vtp| < Vin <= VDD): the PMOS enters cutoff (Vsg=VDD-Vin<|Vtp|, off), while the NMOS remains in the triode region - with no PMOS pull-up current path, the NMOS pulls the output fully to Vout=0V, and the inverter output is in its low logic state.

Conditions for Different Regions of Operation (Summary)

Practical significance of the VTC shape: the CMOS inverter's characteristically sharp, high-gain transition region (Region C) directly gives rise to its excellent noise margins (the range of valid, unambiguous input voltage that is still correctly interpreted as a valid logic-0 or logic-1 by a following gate), since the output remains very close to its full-swing rail value (VDD or 0V) across the wide flat regions (A/B and D/E) on either side of the narrow, steep transition region, meaning the inverter's output is highly insensitive to small input voltage variations except very close to the switching threshold itself - this combination of full rail-to-rail output swing, high transition-region gain, and correspondingly wide, well-defined noise margins is one of the most important reasons CMOS has become the dominant logic family for digital VLSI design, since it provides excellent robustness against noise, process variation, and voltage-supply fluctuations compared to earlier logic families (such as NMOS-only or bipolar TTL logic) that do not achieve full rail-to-rail swing or comparably sharp transition characteristics.

The exact location of the switching threshold voltage Vinv (where Vin=Vout on the VTC, occurring within Region C where both transistors are in saturation) depends on the relative sizing (W/L ratios) of the NMOS and PMOS transistors and their respective process transconductance parameters - for a symmetrically-designed inverter (with PMOS width sized to compensate for the lower hole mobility, typically Wp/Wn approximately equal to mun/mup, roughly 2 to 2.5), the switching threshold is centered close to VDD/2, giving equal noise margins for both logic-0 and logic-1 input interpretation; an inverter with unequal (skewed) sizing shifts Vinv away from VDD/2, trading off noise margin on one side for improved switching speed or reduced area on the other, a design choice sometimes deliberately exploited in speed-critical or area-constrained circuit paths.

The width of the transition region (Region C) itself, and hence the inverter's maximum small-signal gain at the switching point, depends on the channel-length modulation parameter (lambda) of the fabrication process and the transistor sizing - a shorter transition region (steeper VTC slope) generally corresponds to better noise immunity and a more clearly-defined logic threshold, while process scaling to shorter channel lengths tends to increase channel-length modulation effects, somewhat widening the transition region and reducing peak gain compared to an idealized long-channel MOSFET model, an important second-order effect considered in detailed CMOS inverter characterization beyond the basic five-region qualitative analysis presented above.

The CMOS inverter's DC characteristic is typically measured or simulated using a DC sweep analysis, in which Vin is swept slowly and quasi-statically from 0 to VDD while the corresponding steady-state Vout is recorded at each point, producing the VTC curve described above - this DC sweep is distinct from a transient (time-domain) simulation, which would instead apply a fast-changing input waveform and observe the inverter's dynamic switching response including propagation delay and output rise/fall times, a complementary characterization needed to assess the inverter's switching speed rather than merely its static input-output voltage relationship. Both the DC (VTC) and transient (switching-speed) characteristics are essential, complementary aspects of a complete CMOS inverter characterization used in practical standard-cell library development, with the VTC primarily determining noise-margin and logic-level robustness, and the transient response primarily determining the inverter's contribution to overall circuit timing and maximum operating frequency.

Designers also commonly characterize the inverter using its unity-gain points (where the VTC slope equals exactly -1), which define the boundary voltages VIL and VIH used in standard noise-margin calculations, distinguishing these unity-gain boundary points from the single switching-threshold point Vinv where Vin equals Vout.