Q1CMOS Design

Method: Deriving Logic Function from Transistor-Level CMOS Schematic

Any static CMOS logic gate consists of two complementary (dual) networks: a pull-up network (PUN) built entirely from PMOS transistors, connecting the output node to VDD, and a pull-down network (PDN) built entirely from NMOS transistors, connecting the output node to ground, with the two networks always being exact logical duals of one another (wherever the PUN has a series connection, the PDN has a parallel connection at the corresponding position, and vice versa) - this duality guarantees that for every input combination, exactly one of the two networks conducts, giving a well-defined, glitch-free output at all times.

Conduction rules: a PMOS transistor conducts when its gate input is logic-0 (since PMOS is a low-active-gate device); an NMOS transistor conducts when its gate input is logic-1. For a series combination of transistors, the combination conducts only when ALL transistors in the series chain conduct simultaneously (an AND-of-conduction-conditions relationship); for a parallel combination, the combination conducts when ANY transistor in the parallel group conducts (an OR-of-conduction-conditions relationship).

Tracing the Pull-Up (PMOS) Network

Based on the described schematic, the pull-up network from VDD to the output node Y consists of: a PMOS transistor gated by C, in series with a parallel combination of two PMOS transistors gated by A and by B, in series with a further PMOS transistor gated by D.

This pull-up network conducts (pulling Y to logic-1) when: the C-gated PMOS conducts (requiring C=0), AND at least one of the A-gated or B-gated PMOS transistors conducts (requiring A=0 OR B=0), AND the D-gated PMOS conducts (requiring D=0). Expressing this pull-up conduction condition:

Tracing the Dual Pull-Down (NMOS) Network

The pull-down network must be the exact logical dual of the pull-up network: wherever the PMOS network has a series connection, the NMOS network has a parallel connection at that same position, and vice versa. Applying this duality: the series C in the PMOS network becomes a parallel C in the NMOS network; the parallel (A,B) block in the PMOS network becomes a series (A,B) block in the NMOS network; and the series D in the PMOS network becomes a parallel D in the NMOS network - giving an NMOS pull-down structure consisting of a series combination of A and B (gated by A and B respectively), this series-AB block connected in parallel with a single NMOS gated by C, and this entire combination connected in parallel with a further single NMOS gated by D, between the output node Y and ground.

This pull-down network conducts (pulling Y to logic-0) when: the series A-B combination conducts (requiring A=1 AND B=1), OR the C-gated NMOS conducts (requiring C=1), OR the D-gated NMOS conducts (requiring D=1):

Final Logic Function

Combining the pull-down conduction condition (which directly gives the condition under which Y is pulled to 0):

This can be verified as fully consistent with the pull-up condition derived above via De Morgan's theorem: Y=1 iff NOT(AB+C+D)=1 iff AB+C+D=0 iff (A=0 or B=0) and C=0 and D=0, i.e. iff NOT-C AND NOT-D AND (NOT-A OR NOT-B) - exactly matching the pull-up conduction condition derived independently from the PMOS network trace, confirming the two networks are correctly complementary and the derivation is self-consistent.

Result: the circuit implements the logic function Y = NOT(A.B + C + D), a compound 4-input AND-OR-INVERT (AOI) gate, specifically an AOI structure combining a 2-input AND term (AB) with two additional single-variable OR terms (C, D). This type of compound gate is a classic CMOS design technique, since it implements a relatively complex Boolean function (equivalent to a 2-input AND gate followed by a 3-input NOR gate) using only a single stage of 8 transistors (4 PMOS + 4 NMOS), rather than requiring three separate gates (an AND gate plus a 3-input NOR gate, which would require substantially more transistors and introduce additional propagation delay through multiple gate stages) - this ability to directly realize complex AOI/OAI Boolean functions in a single CMOS gate stage is one of the most important advantages of static CMOS logic design over simpler logic families, and is extensively exploited in standard-cell library design to minimize both area and delay for commonly-occurring compound logic functions. It should be noted that this derivation is based on carefully tracing the series/parallel transistor topology as described in the original circuit diagram; a student working from their own copy of the exact circuit schematic should independently verify each transistor's gate connection against the figure to confirm this result before relying on it.