Q2CMOS Design
Question
Q.2. A digital CMOS IC operating at 10MHz clock frequency consumes 100mW power, the same IC operating at 15MHz clock frequency consumes 140mW power. What is the static power consumption of the IC.
Answer
For the given digital CMOS IC (100mW at 10MHz, 140mW at 15MHz), treating total power as static power plus a frequency-dependent dynamic power term (P=Pstatic+k*f), solving the two simultaneous equations gives a dynamic power coefficient k=8 mW/MHz and static power consumption Pstatic=20mW.
Setting Up the Power Model
The total power dissipated by a CMOS digital IC consists of a frequency-independent static (leakage) component and a frequency-dependent dynamic (switching) component, which, to a good first-order approximation over a modest frequency range, scales linearly with clock frequency (since dynamic power P=CV^2f, and for a fixed IC operating at a fixed supply voltage V and fixed effective switched capacitance C, dynamic power is directly proportional to f):
where Pstatic is the frequency-independent static/leakage power, k is a proportionality constant (representing the effective dynamic power consumed per unit of clock frequency, k=C*V^2 in effect), and f is the clock frequency.
Setting Up the Simultaneous Equations
Given: at f1=10 MHz, P1=100 mW; at f2=15 MHz, P2=140 mW.
Solving for k and Pstatic
Subtracting the first equation from the second eliminates Pstatic, directly yielding k:
Substituting k=8 back into the first equation to solve for the static power:
Verification
Checking against the second data point: Pstatic+k15=20+815=20+120=140 mW, exactly matching the given value, confirming the solution's consistency.
Result: the static power consumption of the IC is 20 mW, with a dynamic power coefficient of 8 mW per MHz of clock frequency. This method - using two operating points at different clock frequencies to separate the frequency-independent static component from the frequency-proportional dynamic component - is a standard, practical technique for characterizing a real CMOS IC's power breakdown from simple bench measurements, without needing detailed knowledge of the chip's internal capacitance or transistor count; it directly exploits the linear relationship between dynamic power and clock frequency (at fixed supply voltage) predicted by the fundamental CMOS dynamic power equation, allowing the two unknown model parameters (Pstatic and k) to be uniquely determined from just two independent power-versus-frequency measurements, exactly as solved above using simultaneous linear equations. In a real IC, this static power component would itself further be composed of subthreshold leakage, gate-oxide tunneling leakage, and reverse-biased junction leakage current contributions, which do not depend on switching activity or clock frequency but do depend on temperature, supply voltage, and the specific process technology node used.
In practical CMOS ICs, the measured static power typically also includes a temperature-dependent component, since subthreshold leakage current increases roughly exponentially with rising die temperature - this means the 20mW static power value calculated here would itself represent a snapshot at whatever operating temperature the two frequency measurements were taken, and a designer characterizing a real chip across its full operating temperature range would need to repeat this two-point measurement procedure at multiple temperatures to build a complete static-power-versus-temperature model for accurate system-level power budgeting.