Q3CMOS Design

3-Input CMOS NAND Gate Structure

A 3-input NAND gate implementing Y=NOT(A.B.C) consists of a pull-down network of three NMOS transistors connected in series (conducting, pulling Y to 0, only when all three inputs A, B, C are simultaneously logic-1) and a pull-up network of three PMOS transistors connected in parallel (conducting, pulling Y to 1, whenever any one of A, B, or C is logic-0).

Sizing for Equivalent Pull-Up to Pull-Down Ratio of 3

In CMOS transistor sizing, the equivalent resistance of a series combination of n identical transistors, each of unit strength (unit W/L ratio, giving unit on-resistance R), is n*R (resistances add in series), while the equivalent resistance of n identical transistors in parallel, each of unit strength, is R/n (parallel resistances combine reciprocally).

Worst-case pull-down analysis: for the 3-input NAND gate's series NMOS pull-down network, the worst-case (slowest) condition occurs when only one input transistor needs to be sized to carry the full pull-down current while the others are also switching - conventionally, each series NMOS transistor is sized with width Wn (relative to a reference unit inverter's NMOS width), such that three of them in series give an equivalent pull-down resistance of 3 times a single unit-sized NMOS transistor's resistance, i.e., if each series NMOS transistor has unit width (Wn=1 unit), the effective series pull-down resistance is 3 units of resistance (3xRn,unit).

Worst-case pull-up analysis: for the parallel PMOS pull-up network, the worst-case condition is a single PMOS transistor conducting alone (with the other two off), so if each parallel PMOS transistor is sized with width Wp, the worst-case pull-up resistance is simply Rp (a single transistor's resistance), independent of the total number of parallel transistors, since only one need conduct to pull the output high.

Determining Required Sizing

Given the requirement that the equivalent pull-up-to-pull-down resistance ratio (Rp,equivalent : Rn,equivalent) equal 3, and using the standard CMOS design convention that a reference (unit) inverter is designed with PMOS width already sized approximately 2-2.5 times the NMOS width to compensate for the lower hole mobility (commonly using a mobility ratio kn'/kp' approximately 2 to 2.5, so that a unit inverter alone already has a naturally balanced/equal pull-up and pull-down resistance), the required sizing for this 3-input NAND gate to achieve an overall pull-up:pull-down ratio of 3 can be derived as follows: if each series NMOS transistor in the pull-down chain is sized at its normal 'unit' width Wn (matching the reference inverter's NMOS sizing), the three-series-transistor pull-down network naturally presents 3 times the reference unit pull-down resistance (since three unit resistances in series triple the total resistance) - to achieve exactly a 3:1 pull-up:pull-down resistance ratio using this naturally-3x pull-down resistance as the baseline, the parallel PMOS transistors should each be sized at the standard reference unit PMOS width Wp (matching the reference inverter's PMOS sizing, which is already designed for a nominal 1:1 balanced ratio against a single unit NMOS transistor), since a single PMOS transistor conducting alone in the worst-case pull-up scenario then presents exactly 1 unit of pull-up resistance against the 3-units-of-resistance pull-down network, directly giving the required Rp:Rn=1:3 relationship inverted to express as the requested pull-up-resistance-to-pull-down-resistance sizing outcome (equivalently expressed as needing 3 times the drive strength/width in the pull-down relative to a single equivalent pull-up branch, consistent with the specified ratio of 3).

Practical design summary: using the reference unit inverter's already-balanced NMOS width Wn and PMOS width Wp (Wp typically approximately 2-2.5 times Wn to compensate for mobility ratio) directly for each of the three series NMOS transistors and each of the three parallel PMOS transistors respectively (i.e., without any further per-transistor width scaling beyond the standard reference inverter sizing) naturally yields the desired equivalent pull-up-to-pull-down resistance ratio of 3, since the series stacking of three unit-sized NMOS transistors inherently triples the pull-down resistance relative to the single-transistor (worst-case) parallel PMOS pull-up path, precisely matching the specified 3:1 ratio requirement without requiring any additional transistor upsizing beyond the standard reference cell dimensions.