Q1CMOS Design

(i) SRAM and DRAM Cell

SRAM (Static Random Access Memory) cell: the standard 6-transistor SRAM cell consists of two cross-coupled CMOS inverters (each inverter formed from one PMOS and one NMOS transistor), forming a bistable latch capable of stably holding either of two logic states (0 or 1) indefinitely, as long as power remains applied, without requiring any periodic refresh - the cross-coupling means each inverter's output feeds the other inverter's input, creating positive feedback that reinforces and maintains whichever stable state the cell was last written to. Two additional NMOS access transistors, controlled by a shared word line (WL), connect the cell's two internal storage nodes to a pair of complementary bit lines (BL and BL-bar) during read and write operations - during a write operation, the bit lines are driven with the desired new data value (and its complement) with sufficient drive strength to overpower and flip the cell's existing cross-coupled state; during a read operation, the access transistors are turned on and the small differential voltage that develops on the precharged bit line pair (due to the cell's stored state) is sensed by a sense amplifier to determine the stored bit value. SRAM offers very fast access time and does not require refresh circuitry, but its 6-transistor-per-bit structure makes it substantially less dense (and more expensive per bit) than DRAM, restricting its use primarily to smaller, speed-critical memory applications such as processor cache memory.

DRAM (Dynamic Random Access Memory) cell: the standard DRAM cell consists of just a single access (pass) transistor and a single storage capacitor, storing a data bit as the presence (logic-1) or absence (logic-0) of electric charge on the capacitor - during a write operation, the word line turns on the access transistor, connecting the storage capacitor to the bit line, which is driven to the desired voltage (charging or discharging the capacitor to represent the new data value); during a read operation, the access transistor again connects the (previously precharged) bit line to the storage capacitor, and the small amount of charge sharing between the bit line's own parasitic capacitance and the tiny storage capacitor produces a small voltage change on the bit line, which is detected by a sense amplifier (this read operation is inherently destructive, requiring the sensed value to be immediately written back to restore the cell's original charge). Because the storage capacitor inevitably loses its stored charge over time due to leakage current (through the access transistor's off-state leakage and other parasitic leakage paths), DRAM cells require periodic refresh (a read-then-rewrite cycle performed on every cell at a regular interval, typically every few tens of milliseconds) to prevent data loss, adding refresh-control circuitry complexity and a small periodic power/bandwidth overhead, but the extreme simplicity of the 1-transistor-1-capacitor cell structure gives DRAM a much higher storage density (and lower per-bit cost) than SRAM, making DRAM the dominant technology for large main-memory applications despite its volatility and refresh requirement.

(ii) y = NOT(AB+C) Using Domino Logic

Domino logic implements the AND-OR function AB+C using a single dynamic NMOS pull-down evaluation network, followed by a static CMOS inverter buffer stage to produce the final, properly-buffered, non-inverting domino-style output y=NOT(AB+C).

Precharge phase (CLK=0): the clocked PMOS transistor (gated by CLK) turns on, charging the dynamic output node X up to VDD (logic-1), while the clocked NMOS footer transistor (also gated by CLK, but through the standard domino convention where the footer is enabled only during evaluation) remains off, preventing any pull-down evaluation from occurring prematurely during this precharge phase - during precharge, the internal node X is unconditionally set to logic-1 regardless of the current values of inputs A, B, C.

Evaluate phase (CLK=1): the precharge PMOS turns off, and the footer NMOS turns on, enabling the pull-down evaluation network - the NMOS network implementing AB+C consists of a series combination of NMOS transistors gated by A and B (implementing the AND term), connected in parallel with a single NMOS transistor gated by C (implementing the OR term), between node X and the footer NMOS/ground - if A AND B are both logic-1, or if C alone is logic-1, the pull-down network conducts, discharging node X from its precharged logic-1 value down to logic-0; if neither condition is met, node X remains at its precharged logic-1 value throughout the evaluation phase.

Static inverter buffer and monotonicity: the dynamic node X is followed by a static CMOS inverter, producing the final output y=NOT(X)=NOT(AB+C) - this inverter buffer serves two essential purposes beyond simply matching the desired non-inverted logic polarity: it isolates the sensitive, high-impedance dynamic node X from external loading (preventing charge leakage/sharing corruption from a directly-connected next stage), and it ensures the domino gate's final output y makes only a single, monotonically-rising 0-to-1 transition during each evaluation phase (never a 1-to-0 transition during evaluation, since X can only monotonically fall from precharged-1 toward 0, never rise, during a single evaluation phase) - this monotonic-output property is the defining characteristic that gives domino logic its name and is essential for correctly and reliably cascading multiple domino gates together in a pipeline, since each subsequent domino stage's own NMOS evaluation network correctly requires only monotonically-rising inputs to function correctly without introducing evaluation errors from a spurious, out-of-sequence 1-to-0 input transition.

(iii) NP (Zipper) Domino Logic

NP domino logic (also called Zipper CMOS logic) is a race-free dynamic logic technique, similar in overall philosophy to NORA logic discussed elsewhere in this paper, that alternates N-type domino stages (using an NMOS pull-down dynamic evaluation network, precharged high and discharged conditionally low during evaluation, exactly as in the standard domino gate described above) with P-type domino stages (using a complementary PMOS pull-up dynamic evaluation network, precharged low and conditionally charged high during evaluation) directly cascaded together, without requiring a separate static inverter buffer stage between every single pair of cascaded dynamic gates, as conventional domino logic normally requires.

Why the alternating N/P structure allows direct cascading without inverter buffers: an N-type domino stage's output is precharged high and can only fall (discharge) during evaluation, i.e., it produces only monotonically-falling transitions when viewed without the usual inverter buffer, and correspondingly, when this un-buffered, monotonically-falling output is fed directly as an input to a following P-type stage's PMOS evaluation network (which is precharged low and can only rise during evaluation, and which correctly requires monotonically-falling inputs to evaluate correctly, exactly complementary to how an N-type stage requires monotonically-rising inputs), the signal polarities and monotonicity requirements match up correctly without needing an intervening inverter to restore the 'proper' domino output convention - by alternating N-blocks feeding P-blocks feeding N-blocks and so on throughout the pipeline (the 'zipper' pattern from which the technique gets its alternative name, evoking the interlocking alternation of a zipper's teeth), NP/Zipper domino logic eliminates the static inverter buffer stage that conventional single-polarity domino logic requires between every cascaded gate pair, reducing both the transistor count and the propagation delay per pipeline stage, at the cost of requiring careful, correctly-phased two-phase clocking (similar to NORA logic) to ensure the alternating precharge/evaluate timing between the N-blocks and P-blocks remains correctly synchronized and race-free throughout the entire pipeline.