Q5CMOS Design

(i) y = A.NOT(B).C Using CMOS

The function y=A.NOT(B).C is the complement of a simple 3-input AND function using inputs A, the complement of B, and C - to implement this directly as a static CMOS gate producing y (already in its final, non-inverted-again form, i.e. this expression as given already represents an inverting-type output relative to a positive AND-type pull-down network, following the standard CMOS convention that the NMOS pull-down network implements the AND/OR structure of the true output's complement), the most direct interpretation is that this is realized as an AND-NAND-based static gate: a 3-input NAND-like pull-down structure (series NMOS for A, NOT(B) - requiring an inverter to first generate NOT(B) from B - and C) would produce NOT(A.NOT(B).C) at its immediate output node, which would then need one further inverter stage to produce the true (non-inverted) y=A.NOT(B).C if a fully static, non-inverting realization is specifically required; alternatively, if the gate itself is permitted to directly output the complemented form y'=NOT(A.NOT(B).C) at the natural CMOS gate output (the conventional approach when this expression is itself intended as one part of a larger logic network, using the gate's naturally-inverting property), only the single compound gate plus one inverter (to first generate NOT(B) as an available signal) is required.

The pull-down network for the internal node X consists of three series NMOS transistors gated by A, NOT(B), and C respectively (conducting, pulling X to 0, only when A=1 AND NOT(B)=1 AND C=1, i.e., when A.NOT(B).C=1), with the dual pull-up network of three parallel PMOS transistors gated by the same three signals (conducting, pulling X to 1, whenever any of A=0, NOT(B)=0, or C=0), giving X=NOT(A.NOT(B).C) - a final static inverter stage then produces y=NOT(X)=A.NOT(B).C, with an additional preceding inverter stage required to generate the NOT(B) signal from the primary input B before it can be used to gate the appropriate transistors in the main compound gate.

(ii) 1-Bit Memory Cell Using CMOS

A basic 1-bit CMOS memory cell can be implemented using a cross-coupled pair of CMOS inverters (identical in principle to half of the 6-transistor SRAM cell discussed in an earlier answer in this paper), forming a bistable latch, together with a single NMOS access (pass) transistor controlling when new data can be written into the cell.

The two inverters (INV1 and INV2), each built from a standard PMOS/NMOS pair, are connected in a loop (INV1's output feeds INV2's input, and INV2's output feeds back to INV1's input), creating positive feedback that reinforces and stably holds whichever logic value is currently present at the shared internal node, exactly as in the corresponding SRAM cell's cross-coupled pair discussed in Part C Q1 of this paper - the single NMOS access transistor, controlled by a word line (WL) signal, connects this internal storage node to an external bit line (BL) when WL is asserted, allowing external circuitry to either force a new value onto the storage node (overpowering the cross-coupled feedback during a write operation, using a bit-line driver strong enough to flip the latch's state) or to read the currently-stored value (by sensing the bit line's voltage once the access transistor connects it to the storage node) - when WL is de-asserted, the access transistor isolates the storage node from the bit line entirely, allowing the cross-coupled inverter pair to continue stably holding its stored value indefinitely (as long as power remains applied), independent of the bit line's state.

(iii) y = A XOR B Using Transmission Gate

A compact transmission-gate-based XOR implementation uses two transmission gates (each consisting of one NMOS and one PMOS transistor connected in parallel between the same two terminals, with complementary control signals on their gates) to selectively pass either B or its complement NOT(B) to the output, depending on the value of A.

Structure: an inverter first generates NOT(B) from the input B. Transmission gate TG1, controlled by A (with A driving its NMOS gate and NOT(A) driving its PMOS gate), connects NOT(B) to the output node when A=1 (TG1 turned on, passing NOT(B) through to the output). Transmission gate TG2, controlled by the complement of A (with NOT(A) driving its NMOS gate and A driving its PMOS gate), connects B directly to the output node when A=0 (TG2 turned on, passing B through to the output).

Verification of function: when A=1, TG1 is on (passing NOT(B) to output) and TG2 is off, giving y=NOT(B); when A=0, TG2 is on (passing B to output) and TG1 is off, giving y=B - combining these two cases: y=B when A=0, and y=NOT(B) when A=1, which is exactly the truth table of the XOR function (y=A XOR B), since XOR outputs the true input value when the control input is 0, and the inverted input value when the control input is 1. This transmission-gate-based XOR implementation requires only 6 transistors total (2 for the inverter generating NOT(B), plus 2 transistors each for the two transmission gates), substantially fewer than the 8-12 transistors typically required for an equivalent static CMOS AOI-based XOR gate implementation (as discussed in the corresponding earlier stick-diagram answer regarding XOR gate layout), making the transmission-gate approach the generally preferred, more compact and efficient method for implementing XOR (and the closely related XNOR) functions in practical CMOS digital design.

It is worth noting a further practical consideration common to all three requested circuits: the transmission-gate XOR implementation in part (iii), while more transistor-efficient than a static CMOS AOI-based XOR, produces a somewhat degraded output voltage level in certain input combinations if implemented using only a single NMOS or PMOS pass transistor rather than a full complementary transmission gate, since a lone NMOS pass transistor cannot pass a full, undegraded logic-1 level (due to its own threshold-voltage drop), and a lone PMOS pass transistor cannot pass a full, undegraded logic-0 level for the same reason - this is precisely why the full transmission gate (combining both an NMOS and a PMOS transistor in parallel between the same two terminals) is used rather than a simpler single pass transistor, since the parallel PMOS device passes a full, undegraded logic-1 (compensating for the NMOS device's weakness at passing high levels) while the parallel NMOS device passes a full, undegraded logic-0 (compensating for the PMOS device's corresponding weakness at passing low levels), together ensuring the transmission gate passes both logic levels at full strength regardless of which value is being transmitted.

Similarly, for the 1-bit memory cell of part (ii), it is worth noting that during a write operation, the external bit-line driver circuitry must be designed with sufficient drive strength to overpower the cross-coupled inverter pair's own positive-feedback holding strength and force the internal storage node to the new desired value - this requires the access transistor and the external write driver to be sized considerably stronger (lower on-resistance) than the internal cross-coupled inverters' own transistors, a sizing consideration often expressed as a required cell-ratio or pull-up ratio in practical SRAM/latch cell design, ensuring reliable write operation without requiring an excessively large write-driver circuit.