Question 1

Q.1. (a) Name the various types of buses in 8085 Microprocessor. Explain the …

Accepted Answer

The 8085 microprocessor uses three types of buses - address bus (16-bit, unidirectional, memory/IO addressing), data bus (8-bit, bidirectional, data transfer), and control bus (carries control/status signals); its 40-pin package includes address/data lines, control signals, interrupt pins, serial I/O pins, and power/clock/reset pins, each serving a specific role in the microprocessor's operation.

Question 2

Q.1. (a) Distinguish between the memory mapped I/O & peripheral I/O. [8]

Accepted Answer

Memory-mapped I/O treats peripheral devices as if they occupy locations within the regular memory address space, using memory-reference instructions to access them, whereas peripheral (I/O-mapped) I/O uses a separate, dedicated I/O address space accessed only via the IN/OUT instructions; the 8085 supports several addressing modes - immediate, register, direct, indirect, and implied - each illustrated with representative instruction examples.

Question 3

Q.2. (a) Explain the following instructions of 8085 Microprocessor using suit…

Accepted Answer

LHLD, XTHL, DAA, and DAD are key 8085 data-transfer and arithmetic instructions used respectively for loading a register pair directly from memory, exchanging the stack top with HL, adjusting the accumulator after BCD addition, and performing 16-bit register-pair addition; the 8085 recognizes seven distinct machine cycles (opcode fetch, memory read, memory write, I/O read, I/O write, interrupt acknowledge, and bus-idle/DMA-related cycles) that together make up the execution of its instructions.

Question 4

Q.2. (a) Explain the following instructions of 8085 Microprocessor using suit…

Accepted Answer

LXI, XCHG, SPHL, and LDA are further key 8085 data-transfer instructions for loading a register pair with an immediate 16-bit value, exchanging HL and DE contents, transferring HL into the stack pointer, and loading the accumulator directly from a specified memory address; the timing diagram for LXI Rp, 16-bit data shows three machine cycles (one opcode fetch and two memory read cycles) spanning a total of 10 T-states.

Question 5

Q.3. (a) Write a program in 8085 assembly language to add two 16 bit numbers …

Accepted Answer

The 8085 assembly language program below adds two 16-bit numbers stored in memory using the ADD instruction for the lower bytes and the required ADC instruction for the higher bytes (to correctly propagate any carry), storing the 16-bit result back to memory; the SIM instruction's format uses the accumulator's bits to control interrupt masking (bits 0-2), reset interrupt masks (bit 3), serial output enable/data (bits 6-7), and non-standard bit-4 undefined behaviour per the 8085 datasheet.

Question 6

Q.3. (a) Write a program in 8085 assembly language to copy a block of data by…

Accepted Answer

The 8085 assembly language program below copies a block of data bytes from a source memory area starting at 2051H to a destination area starting at 3051H, with the number of bytes to copy read from memory location 2050H, using a counting loop with the BC register pair; the RIM instruction's format reads back the current interrupt mask status, pending interrupt flags, interrupt enable status, and serial input data, all via a single accumulator read.

Question 7

Q.4. Explain vectored and non-vectored interrupts of 8085. [16]

Accepted Answer

In vectored interrupts, the processor automatically jumps to a fixed, predetermined memory address associated with that specific interrupt when it occurs (as with the 8085's RST 5.5, RST 6.5, RST 7.5, and TRAP interrupts), whereas in non-vectored interrupts, the interrupting device itself must supply the actual response (typically a CALL or RST instruction) onto the data bus during the interrupt acknowledge cycle, with the specific service-routine address thus determined by the external device's response rather than being fixed within the processor itself, as is the case for the 8085's INTR input.

Question 8

Q.4. What are various interrupts available in 8085 Microprocessor? Distinguis…

Accepted Answer

The 8085 provides five hardware interrupts (TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR) plus one software interrupt mechanism (RST 0-7 instructions), with priority TRAP greater than RST7.5 greater than RST6.5 greater than RST5.5 greater than INTR; maskable interrupts (all except TRAP) can be selectively enabled or disabled by software (via EI/DI and SIM), whereas the non-maskable TRAP interrupt cannot be disabled by software and is always recognized, reserved for critical events such as impending power failure.

Question 9

Q.5. (a) Draw the architecture of PIC 8259 indicating different blocks and th…

Accepted Answer

The 8259 Programmable Interrupt Controller (PIC) architecture comprises an Interrupt Request Register (IRR), In-Service Register (ISR), Interrupt Mask Register (IMR), priority resolver, control logic, and a data bus buffer, working together to accept, prioritize, and vector up to eight external interrupt requests to a single processor interrupt input; the 8255 PPI's control word register format uses bit D7 to select between mode-set and bit-set/reset operating modes, defining port group modes (0, 1, or 2) and individual port direction (input/output) in the mode control word, or a specific port-C bit number and set/reset value in the bit set/reset control word.

Question 10

Q.5. (a) List the major components of the 8279 keyboard/display interface and…

Accepted Answer

The 8279 keyboard/display interface comprises a keyboard section (scan generator, return lines, debounce/control logic, FIFO/status registers) and a display section (display RAM, timing/control), together allowing automatic scanned keyboard input and multiplexed LED/display output with minimal processor intervention; the 8254 programmable interval timer contains three independent 16-bit counters, each with its own clock, gate, and output pins, controlled through a shared control word register and data bus buffer, supporting multiple counting modes for timing, counting, and waveform generation applications.

Microprocessors