Q3Microprocessors

(a) Explanation of LHLD, XTHL, DAA, DAD Instructions

LHLD (Load H and L Direct): LHLD 2050H loads register L with the content of memory location 2050H, and register H with the content of the next memory location, 2051H — this instruction directly transfers a 16-bit value from two consecutive memory locations into the HL register pair, using direct addressing for the source memory address. For example, if memory location 2050H contains 3AH and 2051H contains 75H, executing LHLD 2050H results in L=3AH and H=75H, so HL=753AH.

XTHL (Exchange Stack Top with HL): this instruction exchanges the content of the HL register pair with the content of the top two bytes currently on the stack (as pointed to by the stack pointer, SP), without changing the value of SP itself. Specifically, L is exchanged with the memory content at address SP, and H is exchanged with the memory content at address SP+1. For example, if HL=1234H before execution, and the stack top (at SP and SP+1) contains 56H and 78H respectively, after XTHL, HL becomes 7856H, while the stack top now contains 34H and 12H — this instruction is commonly used in subroutines that need to temporarily inspect or modify a value passed via the stack without disturbing the stack pointer itself.

DAA (Decimal Adjust Accumulator): this instruction adjusts the 8-bit value in the accumulator, immediately following a binary addition instruction (such as ADD or ADC), to produce the correct result when the operands represented packed BCD (Binary Coded Decimal) digits rather than pure binary values. DAA operates according to the following rule: if the lower nibble (bits 0-3) of the accumulator is greater than 9, or if the auxiliary carry flag is set, then 6 is added to the lower nibble; subsequently, if the upper nibble (bits 4-7) is now greater than 9, or if the carry flag is set, then 6 is added to the upper nibble as well (i.e., 60H is added to the accumulator). For example, adding the BCD digits 08H and 07H with a plain ADD instruction gives a raw binary result of 0FH, which is not a valid BCD digit — executing DAA immediately afterward adds 6 to correct this to 15H, the correct BCD representation of 8+7=15.

DAA flag behaviour in detail: DAA affects the same flags that any ordinary arithmetic instruction affects — S (sign), Z (zero), AC (auxiliary carry), P (parity), and CY (carry) — but its manner of setting them is specific to the decimal-adjustment operation rather than to the immediately preceding ADD/ADC alone. The auxiliary carry flag AC is set by DAA if the lower-nibble correction (adding 6) itself generates a carry out of bit 3 into bit 4; the carry flag CY is set (and, once set by DAA, is never cleared by DAA even if the preceding instruction had not set it) if either the original addition or the upper-nibble correction generates a carry out of bit 7, which is essential for correctly chaining DAA across multiple byte-pairs in a multi-byte BCD addition routine, since a carry out of one BCD byte pair must be propagated as a carry into the addition of the next, more-significant BCD byte pair. The zero flag Z and sign flag S are set according to the final, corrected value left in the accumulator after DAA completes, reflecting the true corrected BCD result rather than the raw pre-adjustment binary sum.

DAD (Double Add): DAD Rp adds the 16-bit content of the specified register pair (Rp, which may be BC, DE, HL, or SP) to the content of the HL register pair, storing the 16-bit result back in HL, and setting the carry flag if the addition produces a carry out of the most significant bit (bit 15) — notably, DAD is one of the few 8085 arithmetic instructions that operates on register-pair (16-bit) data as a whole, rather than only on 8-bit accumulator values, and it affects only the carry flag (no other flags are affected by DAD), making it useful for 16-bit address/data arithmetic such as incrementing a memory pointer by a variable offset held in another register pair.

Practical use of DAD: because DAD leaves the S, Z, AC, and P flags entirely undisturbed, it can safely be inserted into a program between an earlier flag-setting instruction and a later conditional jump that tests one of those untouched flags, without corrupting the condition being tested — a property not shared by ADD or ADC, both of which affect all five flags. This makes DAD particularly convenient for address computation embedded within loops that also rely on flag-based loop termination, since the 16-bit pointer arithmetic performed by DAD does not interfere with, for instance, a zero-flag test on a separate counter register maintained elsewhere in the same loop.

(b) Machine Cycles of 8085 Microprocessor

A machine cycle in the 8085 is defined as the time required to complete one operation of accessing memory or an I/O device, and every 8085 instruction execution is composed of one or more such machine cycles, with each machine cycle itself comprising a specific number of T-states (clock periods). The 8085 recognizes the following distinct types of machine cycles:

• Opcode fetch: the machine cycle in which the processor fetches the instruction opcode byte from memory (addressed by the program counter) — this is the longest basic machine cycle (typically 4 to 6 T-states), since it may also involve decoding the fetched opcode within the same cycle.
• Memory read: used to read a data or address byte from a memory location other than during an opcode fetch (such as reading an immediate operand byte, or reading data pointed to by HL for a MOV A,M-type instruction) — typically 3 T-states.
• Memory write: used to write a data byte to a memory location — typically 3 T-states.
• I/O read: used specifically to read data from an input port during execution of an IN instruction — typically 3 T-states.
• I/O write: used specifically to write data to an output port during execution of an OUT instruction — typically 3 T-states.
• Interrupt acknowledge: a special machine cycle generated in response to an accepted INTR interrupt request, during which the processor activates INTA-bar to signal the interrupting device to place its response (typically a RST instruction opcode, or a CALL instruction for a full 8-byte vectored response) onto the data bus — typically 6 (or, for a multi-byte interrupt response, up to 12) T-states.
• Bus idle: a machine cycle in which no actual memory or I/O access occurs, but the processor nonetheless requires additional clock cycles for internal operations (such as during a DAD instruction's internal register-pair addition, or while waiting for a HOLD request to be serviced) — typically 2 or 3 T-states depending on the specific instruction.

Every 8085 instruction is executed as a defined sequence of these machine cycles (ranging from as few as one machine cycle, four T-states, for the simplest register-only instructions such as MOV A,B, up to five or more machine cycles for more complex instructions involving multiple memory accesses), and this machine-cycle/T-state breakdown is precisely what determines an instruction's total execution time given the processor's clock frequency, a key consideration in timing-critical 8085 assembly language programming and in constructing instruction timing diagrams such as the one required elsewhere in this question paper.

Representative machine-cycle counts by instruction type: register-only instructions such as MOV A,B or ADD B require just one machine cycle (opcode fetch only, 4 T-states), since no further memory access beyond fetching the single opcode byte is needed. Instructions with an immediate operand, such as MVI A, data or ADI data, require two machine cycles (opcode fetch, 4 T-states, followed by a memory read for the immediate byte, 3 T-states), totalling 7 T-states. Instructions that access memory via HL indirect addressing, such as MOV A,M or ADD M, require two machine cycles (opcode fetch plus one memory read, also 7 T-states in total), since the operand address is already available in HL and only the data byte itself must be fetched. Three-byte direct-addressing instructions such as LDA addr or STA addr require four machine cycles (opcode fetch, two memory reads for the 16-bit address, and one further memory read or write for the actual data byte), totalling 13 T-states. CALL addr, being a three-byte instruction that must additionally push the two-byte return address onto the stack, requires five machine cycles (opcode fetch, two address-byte reads, and two memory writes for the stack push), totalling 18 T-states, making it one of the longest-executing instructions in the 8085 instruction set. This range, from the 4 T-states of the fastest register-only instructions up to the 18 T-states of CALL, illustrates directly how instruction complexity and byte length translate into proportionally longer execution time.