Q9Microprocessors

(a) Architecture of 8259 Programmable Interrupt Controller

The 8259 Programmable Interrupt Controller (PIC) is a support chip designed to manage up to eight independent interrupt request inputs (IR0-IR7) on behalf of a microprocessor such as the 8085 or 8086, resolving priority among simultaneously pending requests and supplying the appropriate vectored response to the processor's single interrupt input, greatly extending the limited number of dedicated interrupt inputs a processor natively provides.

Interrupt Request Register (IRR): stores (latches) all interrupt request lines that are currently requesting service — whenever any of the eight IR0-IR7 input lines becomes active, the corresponding bit in the IRR is set, and this register holds the pending status of each request until it has been serviced or otherwise cleared.

In-Service Register (ISR): keeps track of which interrupt requests are currently being serviced by the processor — when the 8259 grants (vectors) an interrupt to the processor, the corresponding ISR bit is set, and this bit remains set until an appropriate End-Of-Interrupt (EOI) command is later issued (either automatically or explicitly by the servicing routine), which prevents a lower-priority interrupt from being incorrectly granted access while a higher-priority interrupt's service routine is still in progress.

Interrupt Mask Register (IMR): stores the current masking status of each of the eight interrupt request lines — setting a particular bit in the IMR disables (masks) the corresponding IR line, preventing it from being recognized by the priority resolver even if it becomes active, providing the same kind of selective interrupt-masking flexibility at the 8259 level that the 8085's own SIM instruction provides for its three dedicated RST interrupts.

Priority Resolver: examines the IRR, ISR, and IMR together to determine, among all currently pending and unmasked interrupt requests, which single request has the highest priority and should next be granted service, according to the currently configured priority mode (the 8259 supports several selectable priority schemes, including fixed priority, in which IR0 always has the highest priority and IR7 the lowest, and rotating priority, in which the most recently serviced interrupt's priority is moved to the lowest position, giving other pending interrupts a fairer opportunity for subsequent service).

Control Logic: manages the overall sequencing of interrupt recognition and the interrupt-acknowledge handshake with the processor, asserting the INT output line to the processor's interrupt input when a qualifying request is present, and correctly sequencing the multi-byte response (typically a CALL instruction and its associated target address, in an 8085/8086 multi-INTA-cycle interrupt-acknowledge protocol) supplied back to the processor via the data bus buffer during the resulting INTA-bar cycle(s).

Data Bus Buffer: provides the actual bidirectional interface between the 8259's internal registers and the processor's external data bus, used both for the processor to write configuration/command information into the 8259 (during initialization and ongoing operation) and for the 8259 to supply its vectored interrupt response back to the processor during an interrupt-acknowledge cycle.

Command word overview (ICW/OCW): the 8259 is configured and controlled entirely through two categories of command words written by the processor into its internal registers. Initialization Command Words (ICW1-ICW4) are written once, in strict sequence, immediately after system reset, to establish the 8259's basic operating configuration: ICW1 initiates the initialization sequence and specifies whether a single 8259 or multiple cascaded 8259s are present, and whether the interrupt request inputs are edge- or level-triggered; ICW2 specifies the upper bits of the interrupt vector addresses to be supplied to the processor; ICW3 (needed only in a cascaded, multi-8259 configuration) identifies which IR lines connect to slave 8259 devices; and ICW4 specifies additional operating mode details such as whether the surrounding system uses an 8085/8086-style processor bus and whether automatic end-of-interrupt handling is desired. Operation Command Words (OCW1-OCW3), by contrast, can be written at any time during normal running operation (not just during initialization) to dynamically adjust the 8259's behaviour: OCW1 sets or reads the Interrupt Mask Register (IMR) to selectively enable/disable individual IR lines; OCW2 controls End-of-Interrupt commands and the various priority-rotation modes; and OCW3 selects which internal register (IRR or ISR) is returned on a subsequent read operation, and controls the special mask mode and poll mode features. This two-tier ICW/OCW command structure allows the 8259 to be configured once at start-up and then flexibly re-tuned (masking, priority rotation, EOI handling) throughout normal program execution without needing to repeat the full initialization sequence.

(b) Mode Control Word and Bit Set/Reset Control Word Formats of 8255 PPI

(i) Mode Control Word format: the 8255 Programmable Peripheral Interface's control register accepts a single control word that configures its three ports (A, B, C) into one of several operating modes. The mode control word format uses bit D7=1 to select mode-set operation (as opposed to bit set/reset operation, discussed next); bits D6-D5 select the operating mode for Group A (Port A and the upper half of Port C): 00 for Mode 0 (simple I/O), 01 for Mode 1 (strobed I/O), or 1X for Mode 2 (bidirectional strobed I/O); bit D4 sets Port A as input (1) or output (0); bit D3 sets the upper half of Port C as input (1) or output (0); bit D2 selects the operating mode for Group B (Port B and the lower half of Port C): 0 for Mode 0, 1 for Mode 1; bit D1 sets Port B as input (1) or output (0); and bit D0 sets the lower half of Port C as input (1) or output (0).

(ii) Bit Set/Reset Control Word format: when bit D7 of the control word is instead set to 0, the 8255 interprets the control word as a bit set/reset command, used specifically to set or clear an individual bit of Port C (useful, for example, for controlling individual handshaking/control signal lines when Port C bits are being used for strobed or bidirectional I/O handshaking in Modes 1 or 2). In this format, bits D3-D1 specify the particular Port C bit number (0 through 7) to be affected, and bit D0 specifies whether that bit should be set to 1 (D0=1) or reset to 0 (D0=0); bits D6-D4 are not used for this function (typically don't-care). This bit set/reset mechanism allows individual Port C output lines to be toggled directly via the control register, without needing to read the entire Port C register, modify the desired bit in software, and write the whole byte back — a convenient and commonly-used feature when Port C bits serve as individual handshaking or control signals in a strobed I/O application.

Mode 1 and Mode 2 handshaking signals: in Mode 1 (strobed input/output), Port A and Port B each operate as a data port accompanied by specific Port C bits automatically reassigned as dedicated handshaking control lines rather than general-purpose I/O — for strobed input, these include STB-bar (Strobe, an active-low input from the external device indicating that valid data is present on the port), IBF (Input Buffer Full, an output informing the external device that the 8255 has latched the data and the port should not be overwritten yet), and INTR (an output used to interrupt the processor once new data has been strobed in); for strobed output, the corresponding handshaking lines are OBF-bar (Output Buffer Full, indicating the processor has written new data to the port), ACK-bar (Acknowledge, an input from the external device confirming it has accepted the data), and again INTR to signal the processor once the external device has acknowledged receipt. In Mode 2 (strobed bidirectional I/O, available only on Port A), the port combines both input and output handshaking on the same eight data lines, using five Port C bits collectively for OBF-bar, ACK-bar, STB-bar, IBF, and INTR, allowing a single port to alternately transmit and receive data with full handshaking in each direction over a shared bus, which is particularly useful in applications requiring bidirectional strobed communication with a single external peripheral device, such as certain printer or communication-adapter interfaces.