Q1Microprocessors

(a) Types of Buses in 8085 Microprocessor

The 8085 microprocessor communicates with memory and I/O devices through three distinct types of buses, each serving a specific function in the overall system architecture.

Address Bus: a 16-bit, unidirectional bus used exclusively to carry the memory address or I/O port address of the location being accessed by the microprocessor. Being unidirectional, address information always flows outward from the microprocessor to memory/I/O devices, never in the reverse direction. The 16-bit width allows the 8085 to address up to 2^16=65,536 (64K) distinct memory locations, giving it a full 64KB address space. In the 8085's specific pin arrangement, the upper 8 bits of the address (A15-A8) appear on dedicated address lines, while the lower 8 bits (A7-A0) are multiplexed with the data bus (discussed below), requiring external latching circuitry (typically using the ALE signal) to demultiplex the lower address byte at the start of each machine cycle.

Data Bus: an 8-bit, bidirectional bus used to transfer actual data between the microprocessor and memory or I/O devices. Being bidirectional, data can flow either from the microprocessor to memory/IO (during a write operation) or from memory/IO to the microprocessor (during a read operation), over the same physical set of eight lines (AD0-AD7 in the 8085, since these lines are time-multiplexed with the lower byte of the address bus as noted above). The 8-bit width defines the 8085 as an 8-bit microprocessor, meaning it processes data in 8-bit (one-byte) units internally, though it can combine register pairs to handle 16-bit data for addressing and certain arithmetic operations.

Control Bus: comprises a collection of individual control and status signal lines (rather than a single unified multi-bit bus in the same sense as the address/data buses), used to carry timing and control information that coordinates and synchronizes the microprocessor's interaction with memory and I/O devices — this includes signals such as read (RD-bar) and write (WR-bar), which indicate whether the current bus cycle is a read or write operation; ALE (Address Latch Enable), used to indicate when the multiplexed AD0-AD7 lines carry valid address information (versus data); IO/M-bar, which distinguishes whether the current operation addresses memory or an I/O device; and status signals S0 and S1, which together with IO/M-bar allow external circuitry to determine the precise type of machine cycle in progress (opcode fetch, memory read, memory write, I/O read, I/O write, interrupt acknowledge, etc.).

Demultiplexing the AD0-AD7 bus: since the lower-order address byte and the data byte share the same eight physical pins (AD0-AD7), external circuitry is required to separate these two time-multiplexed signals into a genuine 8-bit address bus and a genuine 8-bit data bus usable by ordinary memory and I/O chips. This is accomplished using an octal D-type transparent latch, typically the 74LS373, whose enable input is driven directly by the 8085's ALE output. During T1 of a machine cycle, ALE is high, and the 74LS373 is transparent, so the valid lower-order address byte currently on AD0-AD7 passes straight through the latch onto its output lines, which then form the demultiplexed A0-A7 address bus. When ALE subsequently falls low (at the start of T2), the 74LS373 latches and holds this address value steady at its output for the remainder of the machine cycle, even though the AD0-AD7 lines themselves are by then carrying data instead. This single-latch demultiplexing arrangement, combined with the A8-A15 lines (which are never multiplexed and remain valid throughout the machine cycle), is what allows an 8085 system to present a conventional, stable 16-bit address to memory and I/O devices despite the processor's internal use of a multiplexed bus to reduce its pin count.

Bus contention and tri-state (HOLD) behaviour: all three 8085 buses are implemented using tri-state output drivers, meaning each line can be driven high, driven low, or placed into a high-impedance (floating) third state in which the processor effectively disconnects itself electrically from that line. This tri-state capability is essential whenever another bus master, such as a DMA controller, needs to take over the address, data, and control buses to transfer data directly with memory without processor involvement. When an external device asserts the HOLD input, the 8085 completes its current machine cycle, then floats its address bus, data bus, and the RD-bar/WR-bar/IO-M-bar control lines, and asserts HLDA to acknowledge that the buses have been released. Only one device may actively drive a given bus line at any instant; if the processor and an external device were to drive the same line simultaneously with conflicting logic levels, the result would be bus contention, potentially causing indeterminate logic levels and excessive current flow through the conflicting output stages, which the strict HOLD/HLDA handshake is specifically designed to prevent by ensuring the 8085 fully relinquishes bus control before any other device begins driving it.

Comparison with contemporary 8-bit processors: the 8085's bus architecture is often contrasted with that of contemporaries such as the Motorola 6800/6802 and the Zilog Z80. The Z80, being largely software and pin compatible in spirit with the 8080 lineage, similarly uses a non-multiplexed 16-bit address bus and 8-bit data bus, but does not multiplex address and data together as the 8085 does, instead using its extra pins for additional control signals; the 8085's decision to multiplex the lower address byte with data specifically freed up pins that Intel used to integrate the clock generator and system controller functions directly onto the chip (functions that required separate support chips in the 8080), reducing the minimum chip count needed to build a working microprocessor system. The Motorola 6800, by contrast, uses a fully non-multiplexed bus structure with a single-phase TTL-compatible clock, trading away the pin-count savings of multiplexing for simpler external latching requirements. This comparison illustrates that the 8085's multiplexed-bus, single-supply, on-chip-clock-generator design was a deliberate engineering trade-off aimed at minimizing total system chip count and power supply complexity relative to its immediate predecessor and contemporaries, at the cost of requiring the external address-latching circuitry described above.

(b) Pin Diagram of 8085 Microprocessor

The 8085 is packaged in a 40-pin dual-in-line package (DIP), with its pins organized into the following functional groups:

• Address/Data bus pins (AD0-AD7, A8-A15): AD0-AD7 form the multiplexed lower-order address/data bus (carrying the lower address byte during the early part of a machine cycle, and data during the later part, demultiplexed externally using the ALE signal), while A8-A15 form the dedicated, non-multiplexed higher-order address lines.
• Control and status signals (ALE, RD-bar, WR-bar, IO/M-bar, S0, S1): ALE (Address Latch Enable) marks the instant at which the address is valid on the multiplexed bus; RD-bar and WR-bar are active-low read and write strobe signals; IO/M-bar distinguishes memory operations from I/O operations; S0 and S1 are status outputs further identifying the type of machine cycle in progress.
• Interrupt-related pins (INTR, INTA-bar, RST 7.5, RST 6.5, RST 5.5, TRAP): INTR is the general-purpose (maskable, non-vectored) interrupt request input; INTA-bar is the interrupt-acknowledge output; RST 7.5, RST 6.5, and RST 5.5 are the three vectored, maskable hardware interrupt inputs (in decreasing priority order); TRAP is the highest-priority, non-maskable interrupt input.
• Serial I/O pins (SID, SOD): SID (Serial Input Data) and SOD (Serial Output Data) provide simple single-bit serial data communication capability directly built into the 8085, controlled via the RIM and SIM instructions respectively.
• DMA-related pins (HOLD, HLDA): HOLD is an input by which an external device (typically a DMA controller) requests control of the system buses; HLDA (Hold Acknowledge) is the corresponding output by which the 8085 grants this request, releasing the buses into a high-impedance state.
• Clock and reset pins (X1, X2, CLK OUT, RESET IN, RESET OUT): X1 and X2 connect an external crystal (or RC/LC network) to generate the 8085's internal clock; CLK OUT provides the resulting clock signal for use by other system components; RESET IN is the input used to reset the microprocessor; RESET OUT is an output signal indicating the processor is in a reset state, usable to reset other connected peripheral devices.
• Power supply pins (Vcc, Vss) and READY: Vcc and Vss are the +5V supply and ground reference pins; READY is an input used by slower memory/IO devices to insert wait states, halting the processor's bus cycle until the addressed device signals it is ready to complete the data transfer.

This organized pin layout, combining a multiplexed address/data bus with a comprehensive set of control, interrupt, and DMA-support pins within a compact 40-pin package, was a defining and influential design characteristic of the 8085, enabling relatively simple, low-chip-count microprocessor systems to be built using only the 8085 itself along with a small number of standard latch and peripheral support chips, and is precisely why understanding this pin diagram in detail is foundational to designing or analyzing any 8085-based microprocessor system.