Q10Microprocessors

(a) Major Components of the 8279 Keyboard/Display Interface

The Intel 8279 is a dedicated peripheral chip that simultaneously manages a scanned matrix keyboard input and a multiplexed numeric/alphanumeric LED display output, offloading the repetitive scanning tasks for both functions from the main processor.

• Keyboard scan section (scan counter and return lines): generates the sequential scan signals output on the SL0-SL3 scan lines, cycling through each row of the keyboard matrix in turn, while simultaneously monitoring the RL0-RL7 return lines for a key-closure signal indicating that a particular key at the intersection of the current scan line and a return line has been pressed.
• Debounce and control logic: automatically handles keyboard contact-bounce (the brief, rapid make-and-break electrical noise that occurs when a mechanical key switch is physically pressed) by requiring the detected key-closure to remain stable for two consecutive scan cycles before registering it as a valid keypress, eliminating the need for the main processor or software to implement its own debounce routine.
• FIFO/Sensor RAM and status logic: stores detected, debounced keycodes in an internal 8-byte First-In-First-Out (FIFO) buffer, allowing multiple key entries to be captured and queued even if the processor does not immediately read each one, with an internal status register indicating FIFO fullness/emptiness and any detected error conditions (such as FIFO overrun from too many un-read keypresses accumulating).
• Display RAM and display timing/control section: stores the data to be shown on each of up to sixteen 8-bit display character positions, and generates the multiplexed output scan signals (synchronized with the same underlying scan counter used for keyboard scanning) that sequentially activate each display digit position in turn at a fast enough rate for the human eye to perceive a steady, flicker-free display through the well-known phenomenon of visual persistence.

By handling the entire repetitive keyboard-scanning and display-multiplexing task internally, the 8279 allows the main microprocessor to simply write display data to the chip (which the 8279 then continuously outputs to the display without requiring any further processor attention) and periodically read completed keycodes from the FIFO buffer (typically in response to an interrupt generated by the 8279 when the FIFO is non-empty), substantially reducing the software and processor-time burden that would otherwise be required to implement equivalent keyboard-scanning and display-multiplexing functionality directly in the main processor's own program.

Keyboard modes - 2-key lockout versus N-key rollover: the 8279 supports two distinct keyboard-scanning strategies for handling the situation where more than one key may be pressed at, or near, the same moment, selectable through its keyboard/display mode-set command. In 2-key lockout mode, if a second key is pressed while a first key is still held down, the 8279 recognizes and enters into the FIFO only the first key, ignoring (locking out) the second key until the first is released, and if two keys are found to have been pressed within the same debounce scan cycle such that the ordering cannot be determined, neither is entered until the situation resolves — this simpler mode is adequate for most ordinary keyboard applications where genuinely simultaneous multi-key presses are rare and not functionally significant. In N-key rollover mode, by contrast, the 8279 independently detects and debounces every key on the matrix regardless of how many others are simultaneously held down, entering each newly-pressed key into the FIFO in the order it was pressed, which is necessary for applications such as computer keyboards where meaningful key combinations (for example, Shift held together with a character key, or multiple simultaneously-struck keys in rapid typing) must all be correctly and independently detected rather than having later keys suppressed by an already-held first key.

(b) Pin Diagram and Functional Block Diagram of 8254 Programmable Interval Timer

The Intel 8254 is a programmable interval timer/counter chip containing three fully independent 16-bit down-counters (Counter 0, Counter 1, Counter 2), each of which can be independently configured (via a shared control register) to operate in any of six different counting modes, making the 8254 a versatile building block for generating precise time delays, event counting, and periodic waveform generation in microprocessor-based systems.

Pin diagram groups: the 8254's 24-pin package includes an 8-bit bidirectional data bus (D0-D7) for communication with the host processor; address lines A0-A1 used to select which of the three counters (or the control register) is being accessed for a given read/write operation; RD-bar and WR-bar control signals; a CS-bar (Chip Select) input; and, for each of the three independent counters, a dedicated set of three pins — CLKn (the counting clock input for counter n), GATEn (a control input that enables/disables or otherwise gates the counting operation, with its exact effect depending on the counter's configured mode), and OUTn (the counter's output pin, whose waveform behaviour, whether a single pulse, a square wave, or another pattern, depends on the selected counting mode).

Functional block diagram: internally, the 8254 comprises a data bus buffer and read/write control logic that manages communication with the host processor's bus; a control word register that stores the mode and configuration selected for each counter via a control-word write operation from the processor; and the three independent 16-bit counter blocks themselves, each operating entirely independently of the other two (aside from sharing the same internal data bus for loading count values and reading back current counts), with each counter's specific counting behaviour (whether it counts down once and stops, generates a single output pulse, produces a continuous square wave, or one of the 8254's other supported modes) determined by the mode bits written to that counter's portion of the control word register. This architecture of three independent, individually-configurable 16-bit counters sharing a common host-processor interface is what makes the 8254 broadly useful across a wide range of timing applications within a single microprocessor system — for instance, one counter might be configured to generate a periodic real-time-clock interrupt tick, a second to generate a specific audio-tone frequency, and a third to measure the duration of an external event, all simultaneously and independently within the same single 8254 chip.

Brief overview of the 8254's six counting modes (Mode 0-5): Mode 0 (Interrupt on Terminal Count) causes OUTn to remain low after the count is loaded and go high only once the counter reaches zero, remaining high thereafter until reloaded — commonly used to generate a single interrupt after a programmed time delay. Mode 1 (Programmable One-Shot) causes OUTn to go low on the rising edge of GATEn and remain low for exactly one full count period before returning high, producing a single output pulse of programmable duration triggered by an external gate signal. Mode 2 (Rate Generator) produces a continuous train of narrow negative-going pulses on OUTn, one every N clock periods (where N is the loaded count), making it directly suitable for generating a periodic timing reference such as a real-time-clock tick. Mode 3 (Square Wave Generator) similarly produces a continuous, repeating output, but as a symmetrical (or near-symmetrical) square wave rather than narrow pulses, commonly used to generate an audio tone or a system clock/baud-rate reference. Mode 4 (Software Triggered Strobe) causes OUTn to remain high until the counter reaches zero, at which point it goes low for exactly one clock period before returning high, with counting beginning as soon as the count is loaded (triggered by software rather than by GATEn). Mode 5 (Hardware Triggered Strobe) behaves similarly to Mode 4 in producing a single brief low output pulse upon reaching terminal count, but counting instead begins only upon a triggering edge applied to GATEn, rather than immediately upon the count being loaded. This range of six modes allows a single 8254 counter to be configured for widely differing purposes — a one-time delay, a repeating clock tick, a continuous waveform, or an externally-triggered timing strobe — simply by selecting the appropriate mode bits in that counter's control word.