Q2Microprocessors

(a) Memory-Mapped I/O vs Peripheral (I/O-Mapped) I/O

Memory-mapped I/O: in this scheme, I/O device registers (ports) are assigned addresses within the same overall address space used for memory, so that the microprocessor can access an I/O device using exactly the same memory-reference instructions (such as MOV, LDA, STA) that it uses to access regular memory locations, with no distinct instruction type required for I/O operations. Since I/O devices share the memory's 16-bit address space in this scheme, a portion of the total available memory address range must be reserved/sacrificed for I/O device addressing, reducing the amount of address space available for actual memory, but in exchange, any of the processor's memory-reference instructions and addressing modes (including more powerful indirect and indexed addressing modes, where supported by the processor family) become directly usable for I/O operations, often simplifying complex I/O data manipulation.

Peripheral (I/O-mapped) I/O: in this scheme, I/O devices are instead addressed using a separate, dedicated 8-bit I/O address space (in the 8085, giving up to 256 distinct input and 256 distinct output port addresses), accessed exclusively through the special-purpose IN and OUT instructions, which are distinct from the memory-reference instruction set. Since I/O addressing uses an entirely separate address space from memory, the full 64KB memory address range remains available exclusively for memory use, without any encroachment by I/O device addressing, but the range of instructions available for manipulating I/O data is correspondingly more limited (restricted to the simpler IN/OUT instruction forms, without the fuller range of addressing modes available to memory-reference instructions).

Key differences summarized: memory-mapped I/O uses the same address space and instruction set for both memory and I/O, offering more flexible I/O data manipulation at the cost of reduced available memory address space, while peripheral I/O uses a separate address space and dedicated instructions, preserving the full memory address range but offering a more restricted I/O instruction set; the 8085, in particular, natively supports the peripheral I/O scheme via its IN/OUT instructions and dedicated IO/M-bar control signal (distinguishing I/O bus cycles from memory bus cycles), though a system designer can still choose to implement memory-mapped I/O in an 8085 system simply by decoding I/O device addresses within the normal memory address space and using ordinary memory-reference instructions to access them, since the 8085's IO/M-bar signal is generated automatically by the processor based purely on which instruction type (IN/OUT versus memory-reference) is being executed.

(b) Addressing Modes of 8085 Microprocessor

The 8085 instruction set supports five main addressing modes, each specifying a different method by which an instruction identifies the location of the data it operates upon:

• Immediate addressing: the actual data value is specified directly as part of the instruction itself, immediately following the opcode in program memory — for example, MVI A, 32H loads the immediate 8-bit value 32H directly into the accumulator, and LXI H, 2050H loads the immediate 16-bit value 2050H directly into the HL register pair.
• Register addressing: the operand data is located in one of the processor's internal registers, specified directly by the instruction's register-field encoding — for example, MOV A, B copies the contents of register B into the accumulator, with both operands residing entirely within the processor's internal register set, requiring no memory access at all for the operand itself.
• Direct addressing: the instruction directly specifies the full 16-bit memory address of the operand, embedded within the instruction — for example, LDA 2050H loads the accumulator with the content of memory location 2050H, and STA 3000H stores the accumulator's content directly to memory location 3000H, in each case with the target address given explicitly and completely within the instruction.
• Indirect (register-indirect) addressing: the instruction specifies a register pair whose content is itself the memory address of the actual operand, rather than specifying the address directly — for example, MOV A, M copies the content of the memory location whose address is held in the HL register pair into the accumulator (M is a shorthand notation universally used in 8085 assembly language for '[the memory location addressed by HL]'), and LDAX B loads the accumulator from the memory location addressed by the BC register pair.
• Implied (implicit) addressing: the operand or register involved is implied automatically by the opcode itself, without needing to be separately specified in the instruction at all — for example, CMA (complement the accumulator) always operates specifically on the accumulator without any explicit operand field, and RAL (rotate accumulator left through carry) similarly always implicitly operates on the accumulator and carry flag.

Worked example combining several modes: consider a short sequence intended to double the value at memory location 2500H and store the result at 2600H. First, LDA 2500H (direct addressing) loads the accumulator with the content of 2500H — suppose this location holds 15H, so the accumulator now holds 15H. Next, MOV B, A (register addressing) copies this value into B, giving B=15H. Then ADD B (register addressing) adds B to the accumulator, producing A=2AH (15H+15H=2AH), with the carry flag remaining 0 since no overflow beyond 8 bits occurred. Finally, STA 2600H (direct addressing) stores this result to memory location 2600H. This short trace illustrates how direct and register addressing modes are typically combined within a single working routine, each mode being chosen according to whether the relevant value at that step originates as a memory operand or another register's content.

Instruction length versus addressing mode: the choice of addressing mode directly determines how many bytes an instruction occupies in program memory, which in turn affects the number of machine cycles (and hence execution time) required to fetch and execute it. Implied and register addressing mode instructions (such as CMA, MOV A,B) are typically one-byte instructions, since no additional address or immediate-data byte need be encoded — these are also generally the fastest instructions the 8085 executes, often completing in a single machine cycle of 4 T-states. Immediate addressing mode instructions are two bytes long when the data is 8-bit (such as MVI A, 32H) or three bytes long when the data is 16-bit (such as LXI H, 2050H), since the constant value itself must be embedded in program memory immediately following the opcode. Direct addressing mode instructions (such as LDA 2050H or STA 3000H) are always three bytes long, since a full 16-bit address must be encoded within the instruction, regardless of whether the operand itself is only a single byte. Indirect (register-indirect) addressing mode instructions (such as MOV A,M or LDAX B) are typically only one byte long, since the address is not encoded in the instruction at all but is instead already held in a register pair from an earlier instruction — this compactness is one of the principal practical advantages of indirect addressing, particularly within loops that repeatedly access successive memory locations by simply incrementing the pointer register pair (as, for instance, in a block-copy routine), since the instruction fetching overhead per iteration is minimized compared to repeatedly using direct addressing with different embedded addresses.

Understanding these five addressing modes, and recognizing which mode a given instruction employs, is essential for correctly writing and interpreting 8085 assembly language programs, since the same underlying operation (such as loading a value into a register) can be accomplished via different addressing modes depending on whether the data originates as a constant, another register, a directly-specified memory location, or a memory location computed indirectly through a register pair, with the programmer's choice of addressing mode directly affecting both program size (in bytes) and execution time (in machine cycles/T-states) for a given task.