Q6Microprocessors

(a) 8085 ALP: Copy a Block of Data Bytes

Problem setup: the number of data bytes to be copied is stored at memory location 2050H; the source data block begins at memory location 2051H; the destination block begins at memory location 3051H.

LDA 2050H    ; Load accumulator with the byte count (number of bytes to copy)
MOV C,A      ; Move count into register C
MVI B,00H    ; Clear register B (BC now holds the 16-bit count, with B=0 assuming count <256)
LXI H,2051H  ; HL points to the source block start address
LXI D,3051H  ; DE points to the destination block start address
COPY: MOV A,M    ; Get one byte from source location (addressed by HL)
      STAX D      ; Store this byte to destination location (addressed by DE)
      INX H       ; Increment source pointer
      INX D       ; Increment destination pointer
      DCX B       ; Decrement the 16-bit byte counter (BC)
      MOV A,B     ; Check if BC has reached zero: get B into accumulator
      ORA C       ; OR with C - result is zero only when both B and C are zero
      JNZ COPY    ; If BC is not yet zero, repeat the loop
HLT          ; All bytes copied - stop program execution

Program explanation: the program first reads the byte count from memory location 2050H and places it into the BC register pair (used here as a 16-bit down-counter, with B cleared to zero since the count value, being a single byte read via LDA, cannot exceed 255). It then initializes HL to point to the first byte of the source block (2051H) and DE to point to the first byte of the destination block (3051H). Within the COPY loop, each iteration transfers exactly one byte from the source (addressed indirectly through HL, using MOV A,M) to the destination (addressed indirectly through DE, using STAX D), then increments both pointers (INX H and INX D) to move on to the next byte position in each block, and decrements the BC counter (DCX B) to track how many bytes remain to be copied. Since DCX does not by itself affect any flags in the 8085 (unlike INX/DCX on some other processor families, but consistent with the 8085's specific behaviour), the loop explicitly tests whether BC has reached zero by moving B into the accumulator and logically OR-ing it with C (ORA C) — this OR operation correctly sets the zero flag only when both B and C are simultaneously zero (i.e., the full 16-bit counter is exactly zero), after which the conditional jump JNZ COPY causes the loop to repeat as long as any bytes remain uncopied, and falls through to HLT once the entire specified block has been transferred.

Why DCX (and INX) do not affect flags in the 8085: unlike the 8085's 8-bit increment/decrement instructions (INR and DCR), which do update the S, Z, AC, and P flags (though notably never CY), the 16-bit register-pair increment and decrement instructions INX and DCX leave the entire flag register completely untouched. This design choice reflects the fact that INX/DCX are intended primarily for pointer and counter arithmetic on register pairs used as memory addresses or loop counters, where the programmer generally wants to continue using whatever flag state was established by an earlier, unrelated arithmetic or logical instruction without it being silently overwritten by what is conceptually just an address-bookkeeping operation; it is precisely this behaviour that necessitates the explicit MOV A,B / ORA C zero-test sequence in this program, since DCX B alone gives no direct, flag-based indication of when the BC counter has reached zero, in contrast to how DCR on an 8-bit register would have directly set the zero flag as a side effect.

Practical applications of block-copy routines: this general pattern — read a count, initialize source and destination pointers, then loop transferring one byte per iteration while decrementing a counter — is one of the most fundamental and frequently reused routines in 8085 assembly language programming, forming the basis of tasks such as relocating a program or data table from one memory area to another, transferring data from ROM to a working area in RAM at system start-up, buffering data received from an I/O device before further processing, or duplicating a lookup table for a separate purpose elsewhere in memory. Because the routine's structure depends only on the source and destination addresses and the byte count, all supplied as parameters (whether hardcoded, as here, or passed via registers/stack in a more general-purpose subroutine), the same pattern can be adapted directly into a reusable subroutine callable from multiple points within a larger 8085 program, with only the initial pointer and counter values needing to differ between invocations.

(b) Format of RIM Instruction

The RIM (Read Interrupt Mask) instruction is a single-byte 8085 instruction that reads several pieces of status information — the current interrupt mask settings, pending (latched) interrupt request flags, the overall interrupt-enable status, and the current logic level on the SID (Serial Input Data) pin — into the accumulator in a single operation, providing the complementary 'read' counterpart to the SIM instruction's 'write' (configuration) function.

Bit-field meanings: bit D0 (M5.5), D1 (M6.5), and D2 (M7.5) report the current mask status of RST 5.5, RST 6.5, and RST 7.5 respectively (1 indicating the interrupt is currently masked/disabled, 0 indicating it is enabled) — mirroring, in read-back form, the same mask bits that SIM allows the program to set. Bit D3 (IE, Interrupt Enable) reports whether the overall interrupt enable flip-flop is currently set (1) or cleared (0), reflecting whether the processor's interrupt system as a whole is enabled following the most recent EI/DI instruction or interrupt-service-routine activity. Bits D4 (I5.5), D5 (I6.5), and D6 (I7.5) report the pending (latched) status of each of the three vectored interrupt request lines — a 1 in any of these bits indicates that a request on the corresponding interrupt line is currently pending (has been latched by the processor's internal circuitry, particularly relevant for RST 7.5, which is edge-triggered and latches even a brief pulse until serviced or explicitly reset via the SIM instruction's R7.5 bit). Bit D7 (SID) directly reports the current logic level present on the SID (Serial Input Data) pin at the instant RIM executes, allowing a program to read a single bit of external serial data without requiring any dedicated serial-communication peripheral chip. By executing RIM and then examining the returned accumulator bits using ordinary logical/test instructions, an 8085 program can determine the precise interrupt and serial-input status needed to make informed decisions in interrupt-driven or simple serial-communication application code, all without needing to add any external status-reporting hardware.

Practical role of RIM in reading serial input: since the 8085 offers no dedicated UART and provides only the single SID pin for serial input, a software-driven serial receive routine must sample SID at precisely-timed intervals corresponding to the bit period of the incoming data's baud rate, using RIM to fetch its current value into the accumulator (specifically, isolating bit D7 using a mask operation such as ANI 80H, or by rotating the accumulator so that D7 moves into the carry flag for a conditional test) once per bit period, and assembling the successively sampled bits into a complete received byte. Because RIM simultaneously returns the pending-interrupt and mask-status bits alongside SID, a single RIM call within an interrupt service routine can conveniently be used both to read incoming serial data and to check whether any other vectored interrupt is currently pending, without needing a second, separate status-checking instruction sequence — this dual-purpose nature of RIM (and its counterpart SIM) is characteristic of the compact, minimal-chip-count philosophy underlying much of the 8085's on-chip peripheral functionality, allowing simple serial communication and interrupt-status monitoring to be implemented entirely through the processor's own instruction set.