Q8Microprocessors

Various Interrupts Available in 8085 Microprocessor

The 8085 microprocessor provides five distinct hardware interrupt input pins, in addition to a set of software-invoked interrupt instructions:

• TRAP: the highest-priority interrupt, non-maskable (cannot be disabled by software) and edge-and-level sensitive (requires both a rising edge and a subsequently sustained high level to be recognized, reducing susceptibility to noise-induced false triggering) — vectored to address 0024H, typically reserved for critical situations such as impending power failure, requiring an immediate, guaranteed response regardless of the software's current interrupt-masking configuration.
• RST 7.5: the second-highest-priority interrupt, maskable, and rising-edge sensitive (the request is internally latched upon detecting a rising edge, remaining pending until serviced or explicitly cleared via the SIM instruction's reset bit, even if the input signal itself does not remain high) — vectored to address 003CH.
• RST 6.5: third-priority, maskable, and level-sensitive (the interrupt request must remain active/high at the moment the processor samples it in order to be recognized, unlike the edge-latching behaviour of RST 7.5) — vectored to address 0034H.
• RST 5.5: fourth-priority, maskable, and level-sensitive (similar sampling behaviour to RST 6.5) — vectored to address 002CH.
• INTR: the lowest-priority hardware interrupt, maskable, level-sensitive, and non-vectored (requiring the external interrupting device to supply its own response instruction during the interrupt-acknowledge cycle, as discussed in the corresponding answer on vectored versus non-vectored interrupts) — used when additional interrupt sources beyond the three dedicated RST inputs are needed, typically in conjunction with an external interrupt-controller chip.
• Software (RST 0 - RST 7) instructions: in addition to the hardware interrupt pins, the 8085 instruction set includes eight one-byte RST n instructions (RST 0 through RST 7), which, when executed as part of a running program, cause an immediate unconditional call to the corresponding fixed vector address (8×n), functioning as software-generated interrupts/subroutine calls — commonly used to implement operating-system or monitor-program service calls in simple 8085-based systems.

Maskable vs Non-Maskable Interrupts

Maskable interrupts are those whose recognition by the processor can be selectively enabled or disabled under software control — in the 8085, this applies to RST 7.5, RST 6.5, RST 5.5, and INTR. The overall interrupt system (covering all maskable interrupts collectively) can be globally enabled or disabled using the EI (Enable Interrupts) and DI (Disable Interrupts) instructions respectively, while the SIM instruction (discussed in an earlier answer) additionally allows each of the three RST interrupts to be individually masked or unmasked without needing to disable the entire interrupt system at once — this selective masking capability is useful when a program is executing a critical section of code that must not be interrupted by lower-priority events, while still remaining able to respond to a genuinely urgent condition if needed, or when a program wishes to service some interrupt sources while deliberately ignoring others during a particular phase of its execution.

Non-maskable interrupts cannot be disabled by any software instruction — in the 8085, TRAP is the sole non-maskable interrupt, meaning it will always be recognized and serviced by the processor regardless of the current state of the interrupt-enable flip-flop or any SIM-based masking configuration, precisely because TRAP is intended for genuinely critical situations (most classically, imminent power supply failure, where the system may have only a few milliseconds of residual operating time before power is lost entirely) where it would be unacceptable for the processor to ignore the interrupt due to some unrelated software condition having left interrupts disabled. This distinction between maskable and non-maskable interrupt behaviour reflects a deliberate design trade-off: maskable interrupts provide the software with fine-grained control over exactly when and which interrupt sources are permitted to disturb normal program execution, suitable for the great majority of routine interrupt-driven applications (I/O device servicing, timer events, and similar), while the singular non-maskable TRAP interrupt provides an unconditional, always-available emergency response mechanism reserved specifically for the rare but critical situations where guaranteed immediate processor response, regardless of software state, is essential to correct system operation (such as ensuring critical data is saved to non-volatile memory in the brief window available before a detected power failure actually causes the system to lose power entirely).

Interrupt Priority Resolution

When two or more interrupt requests become active simultaneously, the 8085's internal priority-resolution logic ensures that only the highest-priority pending request among them is actually granted service at that instant, with the fixed priority order being TRAP (highest), followed by RST 7.5, then RST 6.5, then RST 5.5, and finally INTR (lowest). This priority resolution occurs automatically within the processor's interrupt-control circuitry and requires no software intervention: if, for example, both RST 6.5 and RST 5.5 become active at the same time, the processor recognizes and vectors to RST 6.5 first, since it has higher priority, while the RST 5.5 request remains pending (if it is edge-latched) or must still be active at the next sampling point (if level-sensitive) to be serviced afterward. Once a service routine for a given interrupt is in progress, that interrupt and all lower-priority interrupts are automatically disabled by the processor's own interrupt-enable flip-flop being cleared upon accepting the interrupt (unless the service routine explicitly re-enables interrupts with EI), so a lower-priority interrupt occurring during an already-in-progress higher-priority service routine will simply remain pending until the current routine completes and interrupts are re-enabled, whereas a higher-priority interrupt (most notably TRAP, being non-maskable) can still interrupt an already-executing lower-priority service routine even without an explicit EI, precisely because TRAP bypasses the maskable interrupt-enable mechanism entirely. This fixed hardware priority scheme is what makes it essential, at the hardware design stage, to assign each interrupt source in a given application to the 8085 interrupt input whose fixed priority level correctly matches the relative urgency of that source's servicing requirement.

Practical Example Scenario for TRAP

A commonly cited practical use of TRAP is in a power-fail safe-shutdown scheme: external power-monitoring circuitry continuously compares the incoming DC supply voltage against a threshold, and when the voltage begins to sag below this threshold (indicating imminent loss of mains power, well before the system's regulated supply voltage actually drops out of tolerance), this circuitry asserts the TRAP input. Because TRAP is non-maskable, the processor is guaranteed to respond immediately, transferring control to address 0024H regardless of whatever the main program was doing or whether interrupts had been disabled for some unrelated reason. The resulting TRAP service routine then has a brief but guaranteed window (afforded by reserve energy typically held in supply-smoothing capacitors) to save critical processor register contents and any essential working data to non-volatile memory (such as battery-backed RAM or an EEPROM) before the supply voltage decays too far for reliable operation to continue, so that this state can later be restored and normal operation resumed once power is restored — a capability that would not be reliably achievable using any of the maskable interrupt inputs, since a program section that had deliberately disabled interrupts (for example, during a critical, non-interruptible data-transfer sequence) would otherwise cause the power-fail warning to be missed entirely until it was too late to save the data.