Question 1

Q.1. What is the role of Program Counter Register?

Accepted Answer

The Program Counter (PC) register holds the memory address of the next instruction to be fetched and executed, automatically incrementing after each fetch to sequence normal program execution.

Question 2

Q.2. What do you mean by word size for a Computer Machine?

Accepted Answer

Word size refers to the number of bits a computer's CPU processes, transfers, and stores as a single natural unit in one operation, determining the width of its registers, data bus, and typically the size of a single memory-addressable data unit.

Question 3

Q.3. What do you mean by virtual memory?

Accepted Answer

Virtual memory is a memory management technique that gives programs the illusion of a large, contiguous address space by transparently mapping virtual addresses to physical memory (RAM) and secondary storage (disk), allowing programs larger than physical RAM to run and providing memory protection between processes.

Question 4

Q.4. What do you mean by Data Hazards?

Accepted Answer

Data hazards occur in a pipelined processor when an instruction depends on the result of a preceding instruction that has not yet completed and written back its result, potentially causing the dependent instruction to read stale or incorrect data if not properly handled.

Question 5

Q.5. What do you mean by Real mode addressing?

Accepted Answer

Real mode addressing is the original 8086-compatible addressing mode used by x86 processors, in which a 20-bit physical address is formed by combining a 16-bit segment register (shifted left 4 bits) with a 16-bit offset, limiting addressable memory to 1 MB.

Question 6

Q.6. What do you mean by Interrupt?

Accepted Answer

An interrupt is a signal to the processor indicating that an event requiring immediate attention has occurred, causing the CPU to temporarily suspend its current program, save its state, and execute a dedicated interrupt service routine before resuming the original program.

Question 7

Q.7. Explain memory hierarchy in brief.

Accepted Answer

Memory hierarchy organizes computer storage into multiple levels — registers, cache, main memory (RAM), and secondary storage — trading off speed, cost and capacity, with faster, more expensive, smaller-capacity memory closer to the CPU and slower, cheaper, larger-capacity storage farther away.

Question 8

Q.8. Differentiate Parallel ports with Serial ports.

Accepted Answer

Parallel ports transmit multiple bits of data simultaneously over multiple physical wires (higher throughput, but shorter cable range and more susceptible to signal skew/interference), while serial ports transmit data one bit at a time over a single wire pair (simpler cabling, longer range, but lower raw data rate per line).

Question 9

Q.9. What do you mean by memory management unit?

Accepted Answer

A Memory Management Unit (MMU) is a hardware component that translates virtual addresses generated by the CPU into physical memory addresses, and enforces memory protection/access permissions, enabling virtual memory and multi-process memory isolation.

Question 10

Q.10. What do you mean by Multilevel Bus Architecture?

Accepted Answer

Multilevel bus architecture organizes a computer system's interconnection buses into multiple hierarchical levels (e.g., processor/memory bus, system bus, peripheral bus), each optimized for a different speed/distance/device-count requirement, connected through bridges that translate between the different bus levels.

Question 11

Q.1. Differentiate CISC vs. RISC.

Accepted Answer

CISC (Complex Instruction Set Computer) architectures use a large set of complex, variable-length, multi-cycle instructions that can directly operate on memory, while RISC (Reduced Instruction Set Computer) architectures use a small set of simple, fixed-length, single-cycle instructions restricted to a load-store model, generally enabling more efficient pipelining and higher clock speeds at the cost of requiring more instructions to accomplish the same task.

Question 12

Q.2. What is the significance of Control Unit? Explain.

Accepted Answer

The Control Unit is the CPU component that generates the precisely-timed sequence of control signals needed to fetch, decode, and execute each instruction, coordinating the operation of the ALU, registers, memory, and I/O devices, making it essential to the correct, orderly functioning of the entire processor.

Question 13

Q.3. Differentiate hard wired control unit with microprogrammed control unit …

Accepted Answer

A hardwired control unit generates control signals using fixed combinational logic circuits (fast but inflexible), while a microprogrammed control unit generates control signals by sequentially reading pre-stored microinstructions from a control memory (control store), offering greater flexibility and easier modification/debugging at the cost of somewhat lower speed due to the additional control-memory-access overhead.

Question 14

Q.4. Why we use cache memory? Explain.

Accepted Answer

Cache memory is used to bridge the significant speed gap between the very fast CPU and the comparatively much slower main memory (RAM), storing copies of recently and frequently accessed data/instructions in a small, very fast memory located close to (or within) the CPU, exploiting temporal and spatial locality of reference to significantly reduce the average memory access time experienced by the processor.

Question 15

Q.5. Explain DSP Architecture in detail.

Accepted Answer

Digital Signal Processor (DSP) architecture is specialized for efficient, high-speed repetitive numerical computation (particularly multiply-accumulate operations central to digital filtering and signal transforms), featuring a Harvard (separate program/data memory) architecture, dedicated hardware multiplier-accumulator units, specialized addressing modes (circular buffering, bit-reversed addressing), and zero-overhead hardware looping.

Question 16

Q.6. Explain Instruction level pipelining with suitable example.

Accepted Answer

Instruction-level pipelining overlaps the execution of multiple instructions by dividing instruction processing into sequential stages (fetch, decode, execute, memory-access, write-back), with each stage handling a different instruction simultaneously, so that a new instruction can begin every clock cycle, dramatically improving instruction throughput compared to fully sequential (non-overlapped) execution.

Question 17

Q.7. Explain various Addressing modes of 80x86 in detail.

Accepted Answer

The 80x86 architecture supports several addressing modes including immediate, register, direct, register indirect, based, indexed, based-indexed, and based-indexed with displacement, providing flexible ways to specify operand locations for both simple register/immediate operands and complex memory-based data structures (arrays, records).

Question 18

Q.1. What do you mean by pipelining? What are the challenges during implement…

Accepted Answer

Pipelining overlaps the execution of multiple instructions across sequential processing stages to improve instruction throughput, but faces implementation challenges from structural hazards (resource conflicts), data hazards (dependent operand values not yet available), and control hazards (uncertain branch outcomes/targets), addressed through solutions including hardware duplication, data forwarding/stalling, and branch prediction/delayed branching respectively.

Question 19

Q.2. What do you mean by direct memory access? Explain DMA Controller in detail.

Accepted Answer

Direct Memory Access (DMA) is a technique allowing peripheral devices to transfer data directly to/from main memory without continuous CPU involvement, using a dedicated DMA Controller chip that takes over the system bus from the CPU for the duration of the transfer, operating in burst, cycle-stealing, or transparent modes to balance transfer speed against CPU availability.

Question 20

Q.3. (a) What is the role of Page Table? Explain with suitable example.

Accepted Answer

A page table maps virtual (logical) page numbers to physical frame numbers, enabling the virtual memory system to translate CPU-generated virtual addresses into actual physical memory addresses; a microprogram sequencer is the hardware unit within a microprogrammed control unit that determines the address of the next microinstruction to fetch from the control store, supporting sequential, branching, and subroutine-like microprogram execution flow.

Question 21

Q.4. Explain Instruction Set of 80x86 in detail.

Accepted Answer

The 80x86 instruction set comprises data transfer instructions (MOV, PUSH, POP, XCHG), arithmetic instructions (ADD, SUB, MUL, DIV, INC, DEC), logical/bit-manipulation instructions (AND, OR, XOR, NOT, shift/rotate), control-transfer instructions (JMP, conditional jumps, CALL/RET, LOOP), and string-manipulation instructions (MOVS, CMPS, SCAS, using repeat prefixes for efficient block operations).

Computer Architecture