Q1Computer Architecture

CISC (Complex Instruction Set Computer): characterized by a large, rich instruction set including complex instructions that can perform multiple low-level operations (e.g., memory load, arithmetic operation, and memory store) within a single instruction, variable-length instruction encoding (different instructions occupy different numbers of bytes), and instructions that can directly operate on memory operands (not just registers) — this design philosophy aims to reduce the total number of instructions needed to express a given program (since each instruction accomplishes more), historically valued when memory was expensive and compact code size was a priority, and simplifies the compiler's job somewhat since more complex operations map directly to single machine instructions; examples include the x86 architecture.

RISC (Reduced Instruction Set Computer): characterized by a small, simple instruction set, uniform fixed-length instruction encoding (simplifying instruction decoding), and a strict load-store architecture (only dedicated load/store instructions can access memory; all arithmetic/logic instructions operate exclusively on registers) — this design philosophy prioritizes instructions that can each execute in a single clock cycle (or a small, uniform number of cycles), which greatly simplifies and improves the efficiency of instruction pipelining, generally enabling higher clock speeds and better overall throughput despite requiring a larger total number of instructions to accomplish equivalent tasks compared to CISC; examples include ARM and traditional MIPS architectures.

• Instruction complexity: CISC has complex, multi-step instructions; RISC has simple, single-step instructions.
• Instruction length: CISC uses variable-length instruction encoding; RISC uses uniform, fixed-length encoding.
• Memory access: CISC allows arithmetic/logic instructions to directly reference memory operands; RISC restricts memory access strictly to dedicated load/store instructions.
• Cycles per instruction: CISC instructions often take multiple clock cycles; RISC instructions are designed to complete in a single clock cycle (ideally).
• Pipelining efficiency: RISC's uniform, simple instruction format makes pipelining considerably easier and more efficient to implement than CISC's variable-length, variable-complexity instructions.
• Compiler complexity: RISC shifts more of the burden of generating efficient code onto the compiler (since more, simpler instructions must be correctly sequenced), while CISC's richer instruction set can reduce this compiler burden somewhat.
• Code density: CISC generally achieves more compact compiled code size for a given program, since fewer instructions are needed; RISC generally produces larger compiled code size due to needing more instructions.

In practice, the strict distinction between CISC and RISC has blurred considerably in modern processor design — many contemporary x86 (CISC) processors internally translate their complex CISC instructions into simpler, RISC-like micro-operations for actual pipelined execution, combining aspects of both design philosophies to achieve both backward compatibility with the established CISC instruction set and the pipelining/performance benefits associated with RISC-style internal execution.