Q3Computer Architecture

(a) Role of the Page Table

In a paged virtual memory system, both the virtual (logical) address space and the physical memory are divided into fixed-size blocks — virtual pages and physical frames respectively, both typically the same fixed size (e.g., 4 KB). A page table is a data structure, maintained by the operating system and consulted by the hardware Memory Management Unit (MMU), that records the mapping between each virtual page number and the specific physical frame number where that page's actual data currently resides in physical memory (or, alternatively, indicates that the page is not currently present in physical memory at all, having been swapped out to secondary storage).

Address translation process: when the CPU generates a virtual address, this address is split into two parts — a virtual page number (the higher-order bits) and a page offset (the lower-order bits, specifying the specific byte location within that page). The MMU uses the virtual page number to index into the page table, retrieving the corresponding physical frame number; this physical frame number is then combined with the (unchanged) page offset to form the complete physical address actually used to access main memory. Since the offset portion of the address is identical between the virtual and physical address (only the page number portion requires translation), this scheme allows efficient address translation using just a single page-table lookup per memory access (in practice, often accelerated by a Translation Lookaside Buffer, TLB — a small, fast hardware cache of recently-used page-table entries, avoiding the need to access the full page table in main memory for every single memory reference).

Worked example: suppose a system uses 4 KB (2^12 byte) pages, and a virtual address 0x00002050 is generated by the CPU. The lower 12 bits (0x050) form the page offset, and the remaining upper bits (0x00002, i.e., virtual page number 2) are looked up in the page table. If the page table indicates that virtual page 2 is currently mapped to physical frame 7, the resulting physical address is formed by combining physical frame 7 with the same offset 0x050, giving the final physical address used to actually access main memory — this simple example illustrates how the page table enables the operating system to place any given virtual page at an arbitrary physical frame location (or move it later, simply by updating the page table entry), completely transparent to the running program, which continues to reference only its own consistent virtual addresses throughout.

Page faults: if a page table entry indicates that the required virtual page is not currently present in any physical memory frame (having been swapped out to disk, or never yet loaded), the MMU raises a page fault exception, transferring control to the operating system's page-fault handler, which locates the required page's data on secondary storage, loads it into a free (or newly-freed, via a page-replacement algorithm) physical memory frame, updates the page table accordingly, and then resumes the originally faulting instruction, which now completes successfully since the required page is now present in physical memory.

(b) Microprogram Sequencer

A microprogram sequencer is the hardware component within a microprogrammed control unit responsible for determining the address of the next microinstruction to be fetched from the control store (the memory holding the actual sequences of microinstructions that implement each machine-level instruction), analogous in role to how the Program Counter determines the next machine-level instruction address, but operating one level lower, at the microinstruction level.

Functions of the microprogram sequencer: (1) sequential execution — incrementing the control-store address register to fetch the next microinstruction in normal sequence, analogous to simple PC incrementing; (2) branching — supporting conditional and unconditional branches within a microprogram, allowing the microprogram's flow to depend on the current state of processor status flags or other condition inputs (essential, for example, to implement a single microprogram routine that correctly handles both the taken and not-taken outcomes of a machine-level conditional branch instruction); (3) mapping/dispatch — translating the opcode of the newly-fetched machine-level instruction into the starting control-store address of that specific instruction's corresponding microprogram routine (since each distinct machine instruction requires its own specific sequence of microinstructions to implement its particular behavior); and (4) subroutine linkage — supporting microprogram subroutines (common microinstruction sequences shared and reused across multiple different machine-level instructions' microprograms, such as a common memory-address-calculation sequence), requiring the sequencer to save and later restore a microprogram return address, analogous to how a machine-level CALL/RET pair uses the stack to manage subroutine return addresses.

The microprogram sequencer is typically implemented using a combination of an incrementer (for sequential execution), a multiplexer selecting among several possible next-address sources (incremented address, branch target address, mapped dispatch address, or subroutine return address) based on fields within the current microinstruction and the current condition-code inputs, and a small register (sometimes a small stack) for saving microprogram subroutine return addresses — together providing the essential address-sequencing logic that allows a microprogrammed control unit to correctly and flexibly generate the specific ordered sequence of control signals needed to implement each machine-level instruction's full behavior.