Q6Computer Architecture

Instruction-level pipelining is a technique for improving processor throughput by dividing the processing of each instruction into a series of distinct, sequential stages (commonly a 5-stage pipeline: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write-Back (WB)), with dedicated hardware for each stage, allowing multiple instructions to be simultaneously in progress at different stages of the pipeline at any given moment — analogous to an assembly line in a factory, where different workers (stages) simultaneously work on different products (instructions) at different points along the line.

Worked example: consider a sequence of instructions I1, I2, I3, I4 processed by a 5-stage pipeline (IF, ID, EX, MEM, WB). In a non-pipelined processor, each instruction would fully complete all 5 stages before the next instruction begins, requiring 5 clock cycles per instruction (20 cycles total for 4 instructions). In a pipelined processor, once I1 completes its IF stage and moves on to ID, I2 can immediately begin its own IF stage in that same clock cycle (since the IF hardware stage is now free); similarly, once I1 moves to EX and I2 moves to ID, I3 can begin IF — so that after an initial pipeline-fill period, a new instruction both begins and completes (in the WB stage) every single clock cycle. For this 4-instruction example, the pipelined processor completes all 4 instructions in only 8 clock cycles (5 cycles for I1 to fully traverse the pipeline, plus 3 additional cycles for I2, I3, I4 to each complete their final WB stage one cycle apart) rather than the 20 cycles a fully sequential, non-pipelined approach would require — illustrating the substantial throughput improvement pipelining provides, approaching (for a sufficiently long instruction sequence) nearly one instruction completed per clock cycle, compared to one instruction per (number-of-stages) clock cycles for non-pipelined execution.

This pipelined overlap requires each pipeline stage to be handled by independent hardware resources (so that, for example, the fetch-stage hardware processing I2 does not conflict with the execute-stage hardware simultaneously processing I1), and its full benefit can be disrupted by pipeline hazards (structural, data, and control hazards, discussed elsewhere in this paper), which may require inserting pipeline stalls (bubbles) or employing techniques such as data forwarding and branch prediction to maintain the pipeline's throughput advantage in the presence of such hazards.