Q2Computer Architecture

Direct Memory Access (DMA) is a technique that allows certain hardware peripheral devices (disk controllers, network interfaces, sound cards) to transfer blocks of data directly to or from main memory, without requiring the CPU to individually manage and execute each word/byte transfer itself — dramatically improving overall system efficiency for large data transfers, since the CPU would otherwise be forced to spend a very large fraction of its time simply moving data word-by-word between a peripheral device and memory (using a technique called programmed I/O), unable to perform any other useful computation during that entire transfer period.

DMA Controller (DMAC)

A DMA Controller is a specialized hardware chip (or integrated processor sub-block) that manages the DMA transfer process on behalf of the CPU. The CPU initiates a DMA transfer by first programming the DMA controller with the necessary transfer parameters — the source address, destination address, and the total number of words/bytes to transfer — after which the CPU is free to continue executing its own program while the DMA controller independently carries out the actual data transfer.

DMA transfer process: when the DMA controller is ready to perform a transfer (or a portion of one), it asserts a bus request (HOLD/HRQ) signal to the CPU, requesting temporary control of the system's address, data, and control buses; the CPU, upon completing its current bus cycle, releases (tri-states) its own connection to these buses and asserts a bus grant (HLDA/HLDA) signal acknowledging that the DMA controller may now take control; the DMA controller then directly drives the address bus with the appropriate source/destination addresses and manages the necessary read/write control signals to transfer the data directly between the peripheral device and memory, without any involvement from the CPU's own internal instruction-execution circuitry; once the DMA controller has completed its transfer (or the portion it is permitted to transfer in the current bus-ownership period), it releases the bus request signal, returning bus control back to the CPU, and typically also generates an interrupt to notify the CPU that the DMA transfer has fully completed.

DMA Transfer Modes

Burst mode: the DMA controller takes complete control of the system bus and transfers the entire requested block of data in one continuous burst, without releasing the bus back to the CPU until the entire transfer is complete — this achieves the fastest possible transfer rate for the DMA operation itself, but can significantly delay the CPU's own bus access (and hence its own execution progress) for the duration of the entire burst transfer, particularly problematic for large data blocks.

Cycle-stealing mode: the DMA controller transfers only a single word (or a small number of words) each time it gains bus access, then releases the bus back to the CPU for at least one cycle before requesting it again for the next word of the transfer — this significantly reduces the maximum delay imposed on the CPU at any single point (since the CPU never waits more than one 'stolen' cycle at a time), at the cost of a somewhat slower overall DMA transfer completion time compared to burst mode, due to the repeated overhead of bus request/release arbitration between each individual word transferred.

Transparent (hidden) mode: the DMA controller transfers data only during clock cycles when the CPU does not actually need the bus for its own operations (such as cycles when the CPU is performing purely internal computation not requiring any memory access) — this mode imposes essentially no performance penalty on the CPU at all, but achieves the slowest DMA transfer completion rate of the three modes, since transfer opportunities depend entirely on the CPU's own, unpredictable pattern of bus-idle cycles, and is consequently the least commonly implemented of the three modes in practice.

The choice of DMA transfer mode represents a direct trade-off between the speed of completing the DMA transfer itself and the degree of performance impact imposed on the CPU's own concurrent program execution, with the specific mode selected depending on the relative priority of transfer speed versus CPU responsiveness for a given system's actual application requirements.