Q4Computer Architecture
Question
Q.4. What do you mean by Data Hazards?
Answer
Data hazards occur in a pipelined processor when an instruction depends on the result of a preceding instruction that has not yet completed and written back its result, potentially causing the dependent instruction to read stale or incorrect data if not properly handled.
Data hazards arise in pipelined processors when two or more instructions in the pipeline have a data dependency — most commonly, a Read-After-Write (RAW) hazard, where an instruction needs to read an operand that a preceding, not-yet-completed instruction is going to write — such that executing the instructions in the normal pipelined, overlapped manner could cause the dependent instruction to use an incorrect (stale) value rather than the updated result. Data hazards are typically resolved using techniques such as pipeline stalling (inserting bubble cycles until the required data becomes available) or, more efficiently, data forwarding/bypassing (routing the computed result directly from an earlier pipeline stage to the stage that needs it, without waiting for it to be formally written back to the register file).