Q1Computer Architecture

Pipelining, as discussed in an earlier answer, is the technique of dividing instruction execution into multiple sequential stages, allowing several instructions to be simultaneously in progress at different stages, thereby improving overall instruction throughput compared to fully sequential, non-overlapped execution. However, several classes of pipeline hazards can disrupt this smooth overlapped operation if not carefully addressed in the pipeline's design.

Structural Hazards

A structural hazard occurs when two or more instructions simultaneously in the pipeline require the same physical hardware resource at the same time — for example, if instruction fetch and data memory access share a single combined memory unit (as in a simple von Neumann architecture), an instruction's memory-access (MEM) stage could conflict with a later instruction's simultaneous instruction-fetch (IF) stage, since both need to use the same memory port in the same clock cycle.

Solution: the most common solution is to duplicate the conflicting hardware resource — specifically, using a Harvard architecture with separate instruction and data memories/caches (as employed in most modern pipelined processors), eliminating the fetch-versus-memory-access resource conflict entirely; more generally, providing sufficient duplicated functional units (e.g., separate ALUs, multiple register file read/write ports) for any resource that would otherwise be simultaneously needed by multiple pipeline stages.

Data Hazards

As discussed in an earlier answer, data hazards occur when an instruction depends on the result of a preceding, not-yet-completed instruction — most commonly a Read-After-Write (RAW) hazard, where an instruction needs an operand that an immediately preceding instruction has not yet computed and written back to the register file.

Solution: the most efficient solution is data forwarding (also called bypassing), in which the result computed by an earlier instruction's execute stage is directly routed to the input of a later instruction's execute stage in the very next cycle, without waiting for the formal write-back-then-read-again sequence through the register file — implemented via additional forwarding paths and multiplexers in the pipeline's execute stage. Where forwarding alone cannot resolve the hazard quickly enough (such as when a value is not available until after a memory-access stage, e.g., following a load instruction), the pipeline must instead insert a stall (a 'bubble,' pausing the dependent instruction for one or more cycles until the needed value becomes available) — a less efficient but sometimes unavoidable fallback solution, and one reason compilers for pipelined architectures attempt to reorder independent instructions to fill the gap after a load instruction, reducing the frequency of unavoidable load-use stalls.

Control Hazards (Branch Hazards)

A control hazard occurs specifically due to conditional branch instructions, where the pipeline does not yet know, at the time it needs to fetch the next instruction, whether the branch will actually be taken or not (and if taken, what the target address will be), since this determination is not made until the branch instruction itself has progressed further through the pipeline (typically not resolved until its execute stage).

Solutions: several complementary techniques address control hazards: (1) Branch prediction, where the processor makes an educated guess (based on either simple heuristics or, in modern processors, sophisticated history-based prediction algorithms tracking each branch's past behavior) about whether a given branch will be taken, speculatively continuing to fetch and execute instructions along the predicted path — if the prediction later proves correct (as it very often is, for well-predicted branches, achieving well over 90% accuracy in modern predictors), the pipeline suffers no penalty at all, but if the prediction proves wrong, the speculatively-fetched incorrect instructions must be discarded ('flushed') from the pipeline, incurring a penalty of several lost cycles; (2) Delayed branching, an older technique (used in early RISC pipelines) in which the instruction immediately following a branch is defined to always execute regardless of whether the branch is taken (the 'branch delay slot'), giving the compiler an opportunity to fill this slot with a useful, independent instruction rather than simply wasting that pipeline cycle; and (3) Branch target buffers/caches, hardware structures that remember the previously-computed target address of recently-executed branches, allowing the pipeline to begin fetching from the predicted target address immediately, without waiting for the target address to be freshly recalculated on each subsequent execution of that same branch instruction.

Summary: structural hazards are resolved primarily through hardware resource duplication (Harvard architecture, multiple functional units); data hazards are resolved primarily through data forwarding, with pipeline stalling as a fallback where forwarding alone is insufficient; and control hazards are resolved through a combination of branch prediction, delayed branching, and branch target caching, together allowing modern deeply-pipelined processors to maintain high instruction throughput close to the theoretical one-instruction-per-cycle limit despite these various classes of hazards that would otherwise significantly degrade pipeline performance if left unaddressed.