8 questions
1. (a) Develop the relation between Ids and Vds for MOSFET and modify it under channel length modulation. [8]
(b) Draw variation of gate oxide capacitance with Vds. Assume the gate voltage Vgs > Vth. [6]
(c) State the condition of ohmic operation. [2]
1. (a) Find the expression of threshold voltage Vtho and discuss how it modified under body bias. [8]
(b) Discuss any two phenomena in MOSFET from - (i) Hot electron effect (ii) Subthreshold conduction (iii) Narrow channel effect. [4+4=8]
2. (a) Draw NMOS inverter with active load and draw its Transfer characteristic. Also find the expression VIL, VIH, VOL and VOH for it. [10]
(b) Draw y = A + B'C using CMOS. [6]
2. (a) Draw and explain the working of Transmission gate (TG). Use it for 2x1 CMOS multiplexer. [8]
(b) What is transistor sizing? Design a y=ABC CMOS logic such that its equivalent (D/L) of pull up section is 90 and pull down section is 30. [8]
3. (a) Draw following CMOS Ckt - (i) y=A+BC+D (ii) y=A'+B'C' [4+4=8]
(b) Draw the layout of y=AB+CDE CMOS ckt use Euler path in it. [8]
3. (a) What is Latch up Problem? How it can be avoided in CMOS ckts? [8]
(b) State any four DRC rules regarding: (i) Contact size (ii) Metal to Metal line separation (iii) Poly width and (iv) Separation between pdiff and Ndiff. [4x2=8]
4. Draw and explain any two logic Ckt from - (i) NORA logic (ii) DRAM (iii) DOMINO logic (iv) NP logic. [2x8=16]
5. Write short note on any two: (i) VHDL code (ii) FPGA (iii) Custom design (iv) ASIC design. [2x8=16]