Q2VLSI Design

Threshold Voltage Expression, Body Bias Effect, and MOSFET Non-Ideal Phenomena

The zero-body-bias threshold voltage VTHO of an NMOS transistor is derived by requiring the surface potential to reach strong inversion (surface potential = 2phi_F, where phi_F = (kT/q)ln(NA/ni) is the Fermi potential of the p-type substrate). VTHO comprises three physically distinct terms: VFB, the flat-band voltage (accounting for the work-function difference between gate and substrate materials plus any fixed oxide charge); 2phi_F, the band-bending required at the surface to achieve strong inversion; and the depletion-charge term sqrt(2qepsilon_siNA2phi_F)/Cox, which represents the additional gate voltage needed to support the depletion-region charge QB0 = sqrt(2qepsilon_siNA2*phi_F) that forms beneath the gate before inversion charge can accumulate, divided by the oxide capacitance per unit area Cox = epsilon_ox/tox to convert this charge into an equivalent voltage.

When a reverse body-to-source bias VSB is applied (source held at higher potential than the body/substrate for an NMOS device, as is standard practice to keep the source-body junction reverse-biased), the depletion region beneath the channel widens further, requiring additional depletion charge to be supported, which in turn requires additional gate voltage to reach inversion. This is captured by the body-effect equation above, where gamma is the body-effect coefficient. Since VTH increases with increasing VSB, stacked NMOS transistors in a logic gate (where upper transistors see a nonzero source-to-body voltage due to the voltage drop across lower transistors) exhibit a higher effective threshold voltage than the bottom transistor, an effect that must be accounted for in accurate delay and noise-margin analysis of series-connected MOS logic structures.

Hot Electron Effect

The hot-electron effect occurs in short-channel MOSFETs where the lateral electric field near the drain end of the channel becomes very large (due to the short channel length concentrating the full VDS drop over a very small distance). Channel electrons accelerated by this intense field can gain kinetic energy far exceeding the thermal equilibrium value, becoming 'hot' carriers. Some of these hot electrons possess enough energy to surmount the Si-SiO2 interface energy barrier and become injected into the gate oxide, where they can become trapped as fixed oxide charge or interface-state charge near the drain. This trapped charge causes a long-term, cumulative shift in threshold voltage and transconductance (a reliability degradation mechanism), and can also generate substrate current via impact ionization, both effects that worsen as channel lengths are scaled down and lateral fields increase, making hot-carrier degradation one of the primary long-term reliability concerns in deep-submicron CMOS technology.

Subthreshold Conduction

Subthreshold conduction refers to the small but nonzero drain current that flows even when VGS is below VTH, in the regime where the surface is in weak inversion rather than fully off. Rather than the square-law behavior of strong inversion, subthreshold current follows an exponential dependence on VGS, IDS,sub proportional to exp(VGS/(n*VT)), where VT = kT/q is the thermal voltage and n is the subthreshold slope (ideality) factor, typically between 1 and 2 depending on the depletion capacitance to oxide capacitance ratio. This exponential 'subthreshold leakage' current is not merely a curiosity - it is the dominant source of static (off-state) power dissipation in modern low-VTH, low-supply-voltage digital ICs, since a 'logically off' transistor never truly shuts off completely, and this leakage scales the total standby power of very-large-scale, densely-integrated chips containing billions of transistors, making subthreshold leakage control (via multiple-VTH design, power gating, and body biasing) a central concern of modern low-power VLSI design.

The body effect has significant practical implications in digital circuit design beyond the simple stacked-transistor threshold-shift observation made above. In particular, in dynamic and pass-transistor logic circuits where a MOSFET's source terminal is not held at a fixed reference potential (unlike in standard static CMOS gates where NMOS sources are always tied to ground and PMOS sources to VDD), the body effect can cause substantial, signal-dependent threshold-voltage variation that must be accounted for when sizing transistors and estimating worst-case propagation delay, since the effective drive strength of the transistor changes as VSB varies with the signal being processed.

Narrow-channel effect, the third listed phenomenon, arises when the transistor's channel width W becomes comparable to or smaller than the width of the depletion region extending laterally from the channel edges (beneath the field-oxide isolation bounding the active area). In wide-channel devices, this lateral depletion region is a negligible fraction of the total channel width and can be ignored, but as W is scaled down in modern narrow-channel devices, the additional depletion charge contributed by these lateral edge regions becomes a significant fraction of the total depletion charge under the gate, causing the effective threshold voltage to increase above the value predicted by the simple one-dimensional threshold voltage model - this narrow-channel threshold increase is the width-scaling counterpart to the short-channel effect (where threshold voltage decreases as channel length is scaled down due to charge-sharing from the source/drain depletion regions), and both effects must be characterized and compensated for via process-level threshold-adjustment implants in modern scaled CMOS technology to maintain predictable, uniform threshold voltages across transistors of different sizes on the same chip.

Taken together, these non-ideal short-channel and narrow-channel phenomena (hot-electron degradation, subthreshold leakage, and narrow-channel threshold shift) represent the central physical limitations that circuit and process designers must manage as CMOS technology continues to scale to smaller geometries, and understanding their combined effect on threshold voltage, leakage current, and long-term reliability is essential for accurate SPICE-level device modeling (via BSIM and similar industry-standard compact models) used throughout modern digital and analog IC design flows.

These considerations collectively explain why accurate SPICE-level compact models (BSIM3, BSIM4, and their successors) devote enormous mathematical complexity specifically to capturing body-effect, hot-carrier, subthreshold, and narrow-channel behavior with high fidelity, since even small modeling inaccuracies in these effects can translate into large timing and power-estimation errors when applied across a modern chip containing many millions or billions of transistors operating under widely varying local bias conditions.

Foundries therefore characterize and specify separate hot-carrier lifetime, subthreshold slope, and width-dependent threshold parameters for every transistor flavor offered in a given process node, and circuit designers must consult these characterization curves whenever pushing a design toward its absolute performance or reliability limits.