Q3VLSI Design

NMOS Inverter with Active Load: Transfer Characteristic and VIL, VIH, VOL, VOH

In an NMOS inverter with an active (enhancement or depletion) load, the load transistor's gate is tied either to VDD (enhancement load, saturated-load configuration) or to its own source (depletion load), while the driver transistor's gate receives the input Vin and its drain is the output node Vout. Unlike a resistive load, the active load is itself a nonlinear MOSFET, so the transfer characteristic (VTC) must be derived by equating the driver and load currents (KCL: current through load = current through driver, since they are in series) across each combination of operating regions.

For an enhancement-load NMOS inverter, the load transistor's gate-source voltage is fixed at VGS,load = VDD - Vout, so the load remains in saturation for essentially the entire useful output range (since VDD - Vout typically exceeds the load's VDSAT). The load current is therefore ID,load = (k_load/2)*(VDD - Vout - VTH)^2, a constant-ish 'current source' characteristic modulated slightly by Vout. The driver, with VGS,driver = Vin, transitions between cutoff, triode, and saturation as Vin sweeps from 0 to VDD, producing the characteristic VTC breakpoints.

VOH (Output High Voltage)

When Vin = 0 (or Vin < VTH,driver), the driver is cut off (zero current), so no current flows through the load either, meaning there is no IR-type drop across the load device. However, since the load itself is a MOSFET rather than an ideal wire, the output cannot rise all the way to VDD if the load's own gate-source condition would turn it off first; for a standard enhancement-load configuration with the load gate tied to VDD, VOH is limited to VOH = VDD - VTH,load (the output rises until the load's own VGS = VDD - Vout falls to VTH,load, at which point the load itself shuts off, clamping the maximum output voltage) - this VOH < VDD 'threshold drop' penalty is one of the well-known disadvantages of enhancement-load NMOS logic relative to CMOS.

VOL (Output Low Voltage)

When Vin = VDD (driver fully on, strongly driven into triode region since Vout is pulled low), VOL is found by equating the driver's triode current to the load's saturation current: (k_driver)[(VDD-VTH,driver)VOL - VOL^2/2] = (k_load/2)(VDD-VOL-VTH,load)^2. Since VOL is small, the VOL^2/2 term is often neglected for a first approximation, giving VOL ≈ (k_load/k_driver)(VDD-VTH,load)^2 / [2*(VDD-VTH,driver)], showing that VOL is minimized (a better logic-low level) by making the driver transistor's k (aspect ratio) much larger than the load's, i.e., a large driver-to-load ratio, the same 'ratioed logic' design principle used in NMOS-pull-up-resistor inverters.

VIL and VIH (Input Low and High Thresholds)

VIL and VIH are defined as the two points on the VTC where the slope dVout/dVin = -1 (unity gain points), found by differentiating the region-appropriate KCL current-balance equation with respect to Vin and setting the derivative to -1. VIL corresponds to the point where the driver just enters saturation from cutoff (a small increase in Vin from VIL causes Vout to begin dropping with unity or greater gain), while VIH corresponds to the point where the driver transitions from saturation into the triode region as Vin increases further. Solving the unity-gain-slope condition in each region yields closed-form expressions for VIL and VIH in terms of VDD, VTH,driver, VTH,load, and the k_load/k_driver ratio; the exact algebra is lengthy, but the essential result is that both VIL and VIH move to higher values as the driver-to-load ratio increases, widening the noise margins on the '0' side while narrowing them somewhat on the '1' side, illustrating the fundamental design trade-off in ratioed NMOS logic between VOL, noise margins, and static power dissipation (since current flows continuously through the series driver-load stack whenever the driver is on).

CMOS Realization of y = A + B'C

The complement of the target function is y' = (A + B'C)' = A'.(B'C)' = A'.(B+C'). The pull-down network (NMOS, active when y=0, i.e. implements the condition y'=1 conducting a path to ground) is therefore built as a series connection of one NMOS transistor gated by A' with a parallel combination of two NMOS transistors gated by B and C' respectively - since y' = A'.(B+C'), series represents AND and parallel represents OR in the switch-network sense. The pull-up network (PMOS) is the dual of the pull-down network: wherever the PDN has a series connection the PUN has a parallel connection and vice versa, so the PUN consists of a parallel combination of one PMOS gated by A' with a series combination of two PMOS gated by B and C'. Note that since the literals available for direct gating are A, B, and C (not their primed complements, unless additional inverters are used), a small preceding inverter stage generating A' and C' is required, or equivalently the transistors gated by A' and C' are driven by dedicated inverter outputs feeding into the main gate structure - the composite circuit then correctly implements y = A + B'C at the output node where PDN and PUN meet.

It is worth contrasting the enhancement-load NMOS inverter analyzed above with the alternative depletion-load NMOS inverter, in which the load transistor is a depletion-mode device (having a negative threshold voltage, so it conducts even at VGS=0) with its gate tied directly to its own source rather than to VDD. This depletion-load configuration avoids the VOH = VDD - VTH,load penalty entirely, since the load's gate-source voltage remains fixed at zero regardless of Vout, allowing the load to continue supplying current (and hence the output to be pulled essentially all the way to VDD) even as Vout approaches VDD - this was historically the preferred NMOS logic configuration wherever depletion-mode implantation was available in the process, precisely because it eliminates the enhancement-load inverter's VOH degradation.

Beyond the DC transfer characteristic, the driver-to-load ratio (often denoted kR = k_driver/k_load) is the single most important design parameter of any ratioed NMOS inverter, since it simultaneously determines VOL, the noise margins, and the static power dissipation of the gate. A larger kR improves VOL (a lower, better logic-low level) and widens the low-side noise margin, but since current flows continuously through the driver-load series path whenever the driver is on (unlike in CMOS, where no static current path exists in steady state), a larger kR driver transistor also draws more static current and hence dissipates more static power - this fundamental static-power penalty, entirely absent in complementary CMOS logic, is precisely why NMOS-only logic families were superseded by CMOS as power consumption became an increasingly dominant concern in VLSI design from the 1980s onward.

Regarding the CMOS realization of y = A + B'C, it should be further noted that if the design constraint requires the true, non-inverted uncomplemented literals B and C (rather than needing separate inverters to generate B' and C') to be more directly usable in the switch network, an equivalent AOI-gate convention treats the NMOS pull-down network's transistors as being gated directly by the true literals appearing in the SUM-OF-PRODUCTS expression for the complementary function, with the overall gate naturally producing an inverted output at the shared PDN/PUN node - in that convention, an OAI (OR-AND-INVERT) or AOI structure directly yields y' rather than y, and a single explicit inverter stage following the AOI gate recovers the true, non-inverted function y=A+B'C, a common and area-efficient practice throughout static CMOS logic design since compound AOI/OAI gates realize complex Boolean functions with fewer total transistors than would be needed by cascading separate elementary NAND/NOR/inverter gates.