Q1VLSI Design

Ids-Vds Relation for MOSFET, Channel Length Modulation, Gate Oxide Capacitance, and Ohmic Condition

The basic MOSFET drain current equation is derived from the charge-sheet model, where the mobile inversion-layer charge per unit area at a point y along the channel is Qi(y) = Cox[VGS - V(y) - VTH], V(y) being the channel potential at that point relative to the source. The drain current, being the same at every point along the channel by current continuity, is IDS = Wmu_nQi(y)dV/dy. Integrating this expression along the channel length from y=0 (V=0) to y=L (V=VDS) yields the triode-region equation IDS = mu_nCox(W/L)[(VGS-VTH)*VDS - VDS^2/2], valid as long as the transistor remains in the triode (ohmic/linear) region.

As VDS is increased, the inversion charge density at the drain end of the channel, Qi(L) = Cox[VGS - VDS - VTH], progressively decreases, reaching exactly zero when VDS = VGS - VTH = VDSAT, a condition called pinch-off. Beyond this point (VDS > VDSAT), substituting VDS = VDSAT into the triode equation and simplifying gives the saturation-region drain current IDS = (mu_nCox/2)(W/L)*(VGS-VTH)^2, which in the ideal long-channel model is independent of VDS beyond pinch-off, producing a flat IDS-VDS characteristic in saturation.

In a real, finite-length MOSFET, however, the pinch-off point does not remain fixed at y=L as VDS increases beyond VDSAT; instead, the channel physically shortens as the pinch-off point moves toward the source, with the effective channel length reducing from L to L' = L - deltaL, where deltaL grows with (VDS - VDSAT). This phenomenon, called channel length modulation (CLM), causes the saturation current to keep rising slightly with VDS rather than remaining perfectly flat, since IDS is inversely proportional to the effective channel length.

This modified saturation-current equation introduces the channel length modulation parameter lambda (units of 1/V), an empirically extracted parameter inversely related to the channel length L (longer-channel devices show smaller lambda and hence flatter output characteristics, while short-channel devices show pronounced current increase with VDS). Physically, lambda models the finite output resistance ro = 1/(lambdaIDS) of the MOSFET in saturation, a parameter of central importance in analog amplifier design since it directly sets the maximum achievable intrinsic voltage gain (gmro) of a single transistor.

Gate Oxide Capacitance Variation with VDS

The gate-to-channel (oxide) capacitance Cgc is not constant across all operating regions but varies with the terminal voltages because the underlying MOS structure's capacitance depends on which of accumulation, depletion, or inversion condition exists beneath the gate. With VGS > VTH so the channel is in strong inversion (as stated in the question), the relevant variation is with VDS at fixed VGS > VTH: in the cutoff/subthreshold region the capacitance would be dominated by the depletion capacitance, but since the device is biased in strong inversion here, in the triode region (small VDS) the full gate oxide capacitance CoxWL is essentially shared equally between the gate-to-source and gate-to-drain overlap-plus-channel capacitances (Cgs ≈ Cgd ≈ CoxWL/2), giving a large total gate capacitance.

As VDS increases toward and beyond VDSAT into the saturation region, the channel pinches off near the drain, electrically disconnecting the drain end of the channel from the gate capacitively; the charge-partitioning models (commonly the 40/60 or similar partition used in SPICE-level MOSFET models) then assign roughly 0% of the channel charge to Cgd (only the small overlap capacitance remains) and about 2/3 (or a similarly weighted majority) of the total channel charge to Cgs. Consequently, as VDS is swept from zero (triode) into saturation, Cgd falls sharply from about CoxWL/2 down to just the gate-drain overlap capacitance, while Cgs approaches a value close to (2/3)CoxW*L, so a plot of gate capacitance versus VDS shows Cgs rising and Cgd falling as VDS crosses VDSAT, with the total gate capacitance Cgc = Cgs + Cgd settling to a lower combined value in deep saturation than in the triode region.

Condition for Ohmic (Triode) Operation

A MOSFET operates in the ohmic (also called triode or linear) region whenever the gate-to-source voltage exceeds threshold (VGS > VTH, so a conducting channel exists) AND the drain-to-source voltage remains below the overdrive voltage, i.e., VDS < (VGS - VTH) = VDSAT. Under this condition, the channel exists continuously from source to drain without pinch-off, and the device behaves approximately as a voltage-controlled resistor for small VDS, which is why this region is also called the resistive or linear region - this is the operating condition explicitly assumed for the small-VDS gate-capacitance discussion above.

It is instructive to note the practical significance of channel length modulation in circuit design: while the ideal square-law model predicts a MOSFET behaves as a perfect current source in saturation (infinite output resistance), the lambda term means every real transistor has finite output resistance ro, which directly limits the maximum voltage gain obtainable from a single common-source amplifier stage to roughly gm*ro. As technology scales to shorter channel lengths, lambda increases (since deltaL becomes a proportionally larger fraction of the now-smaller L), causing ro to shrink and intrinsic gain per stage to degrade, which is one of the central reasons modern analog circuit design in deep-submicron CMOS increasingly relies on cascode structures and multi-stage gain-boosting techniques rather than simple single-transistor amplifier stages.

Regarding gate oxide capacitance behavior, it is also worth emphasizing that this VDS-dependent partitioning of the total gate capacitance between Cgs and Cgd (via the charge-sharing models used in circuit simulators such as SPICE) has direct consequences for high-frequency and transient circuit analysis: because Cgd shrinks substantially once the device enters saturation, the Miller-multiplied effect of Cgd on the effective input capacitance of an inverting amplifier stage is much smaller in saturation than it would be if the device were biased in the triode region, an important consideration when estimating propagation delay and bandwidth in cascaded digital or analog CMOS stages.

Finally, the ohmic (triode) operating condition VDS < VGS - VTH is the regime in which a MOSFET is most commonly used as a pass transistor or as the pull-down/pull-up device of a digital logic gate driving a small output voltage swing, since in this region the device presents a well-defined, gate-voltage-controllable channel resistance rather than acting as a current source - this resistive behavior is precisely what is exploited in ratioed logic families (such as the NMOS active-load inverter discussed elsewhere in this examination) where the driver transistor is deliberately operated deep into the triode region to pull the output down to a well-defined low logic level.