Q8VLSI Design

VHDL Code and FPGA (Field Programmable Gate Array)

VHDL (VHSIC Hardware Description Language, where VHSIC stands for Very High Speed Integrated Circuit) is a standardized hardware description language (IEEE 1076) used to describe, simulate, and synthesize digital electronic circuits and systems, ranging from simple combinational gates to complete processors. A VHDL design is organized around the entity/architecture pairing: the entity declaration defines the external interface of a design unit (its input and output ports and their types), while one or more architecture bodies associated with that entity describe its internal behavior, either structurally (as an interconnection of component instances), behaviorally (as an algorithmic description using processes, signal assignments, if/case statements, closely resembling ordinary sequential programming), or as a dataflow description (concurrent signal assignment statements).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and_gate is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           y : out STD_LOGIC);
end and_gate;

architecture Behavioral of and_gate is
begin
    y <= a and b;
end Behavioral;

This short example illustrates the two-part entity/architecture structure for a simple 2-input AND gate: the entity block declares the interface (two STD_LOGIC input ports a and b, and one STD_LOGIC output port y), while the architecture block (named Behavioral here, though any identifier may be used) provides the actual logic implementation, in this case using a single concurrent dataflow-style signal assignment. Once written, such VHDL code can be simulated (to verify correct logical behavior against a testbench, before committing to hardware) and subsequently synthesized (translated by synthesis tools into an actual gate-level netlist targeting either an FPGA's programmable logic fabric or a full-custom/ASIC standard-cell library), which is precisely why VHDL has become the dominant language (alongside Verilog) for describing digital hardware throughout the modern chip design industry, spanning simple glue logic up to full microprocessor designs.

FPGA (Field Programmable Gate Array)

An FPGA is a reconfigurable semiconductor device containing a large array of programmable logic blocks (commonly called Configurable Logic Blocks or CLBs, each internally built from one or more Look-Up Tables (LUTs) capable of implementing arbitrary combinational logic functions of a small number of inputs, plus flip-flops for sequential storage), a rich programmable interconnect fabric of wires and configurable switch matrices allowing arbitrary routing between logic blocks, and dedicated I/O blocks at the periphery for interfacing with external signals. Unlike an ASIC (Application-Specific Integrated Circuit), whose logic function is permanently fixed at fabrication time by the specific mask set used, an FPGA's logic function is determined entirely by a configuration bitstream loaded into on-chip configuration memory (typically SRAM-based, meaning the configuration must be reloaded every power-up, though some FPGA families use non-volatile flash or antifuse configuration memory instead), which programs the LUT contents and interconnect switch settings to realize whatever specific digital circuit the designer has synthesized.

This reconfigurability gives FPGAs their key advantages of rapid design turnaround (no fabrication lead time - a new or corrected design can be tested within minutes of synthesis completing, versus the weeks-to-months fabrication cycle and enormous non-recurring engineering cost of a new ASIC mask set) and field-upgradability (a deployed FPGA-based product can have its function changed or bug-fixed by simply loading a new configuration bitstream), at the cost of lower maximum clock speed, higher per-unit cost at high production volumes, and higher power consumption per logic function compared to a full-custom ASIC implementing the identical function, since FPGAs must include substantial programmable-interconnect and configuration-memory overhead not needed in a fixed, hardwired ASIC - this fundamental FPGA-versus-ASIC trade-off (flexibility and fast turnaround versus raw performance and per-unit cost at scale) is precisely why FPGAs are favored for prototyping, low-to-medium production volumes, and designs requiring post-deployment reconfigurability, while ASICs remain favored for extremely high production volumes where per-unit cost and maximum performance dominate the design decision.

Custom design and ASIC (Application-Specific Integrated Circuit) design represent the opposite end of the design-methodology spectrum from FPGA-based implementation discussed above. In a full-custom design flow, every transistor's size, placement, and interconnect routing is individually hand-crafted (or at minimum, hand-tuned following automated initial placement) by the circuit designer to achieve the maximum possible area efficiency, speed, and power efficiency for a specific target function - this labor-intensive approach is typically reserved for the most performance-critical or highest-volume circuit blocks (such as microprocessor datapath elements, high-speed SRAM/cache arrays, or standard-cell library elements themselves) where the substantial engineering effort is justified by the resulting silicon area, speed, or power advantage multiplied across enormous production volumes.

ASIC design, more broadly, refers to any integrated circuit designed and fabricated for one specific application (as opposed to a general-purpose, off-the-shelf device such as a standard microprocessor or FPGA usable across many different applications), and encompasses a spectrum of design styles from full-custom (described above) through standard-cell-based design (where the design is composed from a library of pre-characterized, pre-laid-out logic cells - inverters, NAND/NOR gates, flip-flops, and similar - assembled and automatically placed-and-routed by CAD tools based on a synthesized gate-level netlist) to gate-array-based design (where a partially-fabricated wafer containing a regular array of uncommitted transistors is customized only in its final metal interconnect layers, offering faster turnaround and lower non-recurring engineering cost than full-custom or standard-cell design, at some area and performance penalty).

The standard ASIC design flow proceeds through several well-defined stages: specification and architectural design, RTL (register-transfer level) coding in a hardware description language such as VHDL or Verilog, functional simulation and verification against the specification, logic synthesis (translating the RTL description into a gate-level netlist using cells from a target standard-cell library, optimized for the specified timing, area, and power constraints), physical design (floorplanning, placement, clock-tree synthesis, and routing), physical verification (design rule checking as discussed in relation to another question in this examination, along with layout-versus-schematic verification), and finally mask generation and fabrication (tape-out). Compared to the FPGA-based approach, ASIC design offers superior performance, power efficiency, and per-unit cost at high production volumes, but at the expense of a far longer design and fabrication turnaround time, substantially higher non-recurring engineering cost (mask sets for advanced process nodes can cost millions of dollars), and the complete inability to modify the design's function after fabrication - trade-offs that make the FPGA-versus-ASIC (or more generally, the reconfigurable-versus-fixed-function) decision one of the most consequential early architectural choices in any digital system design project.

prompting most modern design teams to adopt FPGA prototyping during early development before committing to a final ASIC implementation for volume production.