Question 1

Define instruction execution cycle.

Accepted Answer

The instruction execution cycle is the strict architectural sequence of Fetching, Decoding, Executing, and Storing an instruction executed continuously by the CPU.

Question 2

What is the difference between hardwired and microprogrammed control units?

Accepted Answer

Hardwired control utilizes fixed silicon logic gates for speed, whereas Microprogrammed control utilizes a ROM to store modifiable micro-instructions for flexibility.

Question 3

Explain the principle of locality of reference.

Accepted Answer

Locality of reference is the mathematical principle stating that CPUs tend to repeatedly access a heavily clustered, restricted set of memory addresses.

Question 4

What is a pipeline hazard?

Accepted Answer

A pipeline hazard is a severe architectural conflict that prevents the next instruction from executing in its designated clock cycle, stalling the pipeline.

Question 5

Differentiate between RISC and CISC architectures.

Accepted Answer

RISC utilizes a small set of simple, single-cycle instructions, while CISC utilizes a massive set of complex, multi-cycle instructions executing complex memory operations.

Question 6

Define hit ratio and miss penalty in cache memory.

Accepted Answer

Hit ratio is the probability of finding data in the cache, while miss penalty is the massive time delay incurred when fetching missing data from RAM.

Question 7

What is direct memory access (DMA)?

Accepted Answer

DMA is a specialized hardware architecture that allows high-speed I/O devices to mathematically read/write directly to RAM, completely bypassing the CPU.

Question 8

Describe Amdahl's Law briefly.

Accepted Answer

Amdahl's Law mathematically calculates the absolute maximum theoretical performance improvement of a system when only a specific fraction of the system is optimized.

Question 9

What is virtual memory?

Accepted Answer

Virtual Memory is an OS/hardware architecture that mathematically illusions a massive continuous RAM space by utilizing the hard drive for swapped data.

Question 10

What is bus arbitration?

Accepted Answer

Bus Arbitration is the strict hardware protocol used to resolve conflicts when multiple master devices simultaneously request control of the shared system bus.

Question 11

Explain Flynn's taxonomy of computer architecture with suitable examples.

Accepted Answer

A detailed exposition of Flynn's Taxonomy, mathematically categorizing computer architectures into SISD, SIMD, MISD, and MIMD based on instruction and data stream concurrency.

Question 12

Discuss the various addressing modes used in CPU with examples.

Accepted Answer

A rigorous breakdown of CPU Addressing Modes, explaining how Immediate, Direct, Indirect, and Indexed modes mathematically dictate how the CPU calculates the Effective Address of an operand.

Question 13

Describe the operation of a set-associative cache mapping technique.

Accepted Answer

A detailed technical exposition of Set-Associative Cache mapping, explaining how it mathematically fuses the high speed of Direct Mapping with the high hit ratio of Fully Associative mapping to eradicate conflict misses.

Question 14

What are data hazards in pipelining? How can they be resolved using operand f…

Accepted Answer

A critical review of Data Hazards in instruction pipelining, explicitly detailing Read-After-Write (RAW) conflicts and mathematically demonstrating how Operand Forwarding (Bypassing) completely eradicates pipeline stalls.

Question 15

Write a short note on interrupt-driven I/O vs programmed I/O.

Accepted Answer

A definitive comparison of I/O transfer architectures, contrasting the CPU-wasting polling mechanisms of Programmed I/O against the highly efficient, asynchronous hardware signaling of Interrupt-Driven I/O.

Question 16

Explain page replacement algorithms like LRU and FIFO.

Accepted Answer

An algorithmic breakdown of Page Replacement in Virtual Memory, contrasting the primitive FIFO queue against the mathematically superior, temporal-locality-based LRU algorithm.

Question 17

Discuss IEEE 754 standard for floating-point representation.

Accepted Answer

A deep dive into the IEEE 754 standard, explaining how it mathematically segments a 32-bit binary structure into Sign, Exponent, and Mantissa to achieve massive dynamic range for floating-point calculations.

Question 18

Explain the architecture and functioning of a Microprogrammed Control Unit in…

Accepted Answer

An exhaustive architectural analysis of Microprogrammed Control Units. Violently contrasts their ROM-based micro-instruction sequencing against rigid Hardwired logic, highlighting the massive advantages in CISC flexibility and complex instruction execution.

Question 19

Discuss memory hierarchy in a modern computer system. Explain how cache memor…

Accepted Answer

A massive theoretical exposition on the Memory Hierarchy. Violently explains the cost/speed mathematical trade-offs, and details how the Principle of Locality empowers L1/L2/L3 Cache architectures to radically multiply overall CPU throughput.

Question 20

Explain instruction pipelining in detail. What are the different types of pip…

Accepted Answer

A critical engineering breakdown of Instruction Pipelining. Violently details the 5-stage architecture, categorizes Structural, Data, and Control Hazards, and executes mathematical solutions like Operand Forwarding and Branch Prediction to maintain throughput.

Question 21

Describe Booth's multiplication algorithm for signed numbers with a suitable …

Accepted Answer

A meticulous mathematical dissection of Booth's Multiplication Algorithm. Proves how shifting over blocks of 1s aggressively reduces the number of ALU additions required to multiply massive signed 2's complement binary integers.

Question 22

Explain various bus arbitration schemes (Daisy chaining, Polling, Independent…

Accepted Answer

An architectural review of Bus Arbitration schemes. Contrasts the strict hardware priority of Daisy Chaining against the software-driven Polling, and details the high-speed Independent Requesting architecture required for modern multi-core systems.

Computer Architecture and Organization