Q20Computer Architecture and Organization

Instruction Pipelining is the absolute foundational architectural technique used to achieve massive CPU parallelism. In a primitive non-pipelined CPU, an instruction must completely finish its 5-stage lifecycle (Fetch, Decode, Execute, Memory, Write-Back) before the next instruction can begin. Pipelining mathematically overlaps these stages. While Instruction 1 is Executing, the hardware is simultaneously Decoding Instruction 2, and Fetching Instruction 3. Ideally, a pipelined CPU outputs exactly 1 completed instruction every single clock cycle, violently multiplying throughput.

However, perfect overlapping is mathematically impossible due to Hazards—conflicts that force the hardware to violently stall the pipeline, injecting dead clock cycles (Bubbles) and destroying performance.

1. Structural Hazards

Occur when the physical silicon lacks the hardware resources to execute two overlapping stages simultaneously. - Example: Instruction 1 is in the Memory stage attempting to write to RAM. Instruction 4 is in the Fetch stage attempting to read from RAM. If the CPU only has one unified memory bus, a catastrophic collision occurs.

2. Data Hazards

Occur when instructions exhibit strict mathematical data dependency. - Example (RAW): ADD R1, R2, R3 followed immediately by SUB R4, R1, R5. The SUB instruction absolutely requires the updated value of R1, but the ADD instruction hasn't reached the Write-Back stage yet.

3. Control (Branch) Hazards

The absolute most catastrophic hazard. When the CPU encounters a conditional BRANCH instruction, it does not mathematically know if the branch will be taken until the Execute stage. However, the Fetch stage has already blindly loaded the next sequential instructions into the pipeline. If the branch is taken, the CPU must violently flush the entire pipeline, destroying all the work done.

• Resolving Structural Hazards: The architecture is physically duplicated. The Harvard Architecture physically separates the Instruction Cache from the Data Cache, mathematically ensuring the Fetch stage and Memory stage can never collide on the bus.
• Resolving Data Hazards: - Operand Forwarding (Bypassing): Internal hardware wires immediately route the mathematical result from the ALU output directly back to the ALU input for the next cycle, completely bypassing the slow Write-Back stage. - Instruction Scheduling: The compiler aggressively analyzes the code and physically reorders instructions, inserting independent tasks between dependent ones to hide the latency.
• Resolving Control Hazards: - Branch Prediction: The CPU utilizes massive hardware arrays (Branch History Tables) to mathematically guess whether a branch will be taken based on past behavior. If the guess is correct (often >95% accurate), zero stalling occurs. - Delayed Branching: The compiler forces a useful, non-dependent instruction into the slot immediately following the branch. This instruction is mathematically guaranteed to execute regardless of the branch outcome, completely eliminating the dead clock cycle.