Q22Computer Architecture and Organization

In a modern architectural layout, multiple "Bus Masters" (e.g., the CPU, DMA controllers, GPU) share a single unified System Bus. If two Masters attempt to aggressively drive electrical signals onto the data lines simultaneously, catastrophic data corruption occurs. Bus Arbitration is the rigid mathematical hardware protocol utilized to determine exactly which Master gains exclusive control of the bus at any given millisecond.

A highly structured, decentralized hardware scheme relying on strict physical wire routing.

• Architecture: A single Bus Grant (BG) wire snakes out of the Arbiter. It physically enters Master 1. If Master 1 doesn't need the bus, the wire physically loops out of Master 1 and into Master 2, and so on, forming a massive chain.
• Mechanism: When any device asserts the global Bus Request (BR) line, the Arbiter asserts the BG line. The signal physically hits Master 1 first. If Master 1 requested it, it intercepts the signal and blocks it from moving down the chain. If Master 1 didn't request it, it passes the signal to Master 2.
• Merit: Extremely simple hardware. Minimal wires required.
• Demerit: Rigid, mathematically fixed priority based purely on physical distance from the Arbiter. Master 10 suffers from catastrophic Starvation if Master 1 constantly requests the bus. Furthermore, if a single wire breaks in Master 3, the entire chain violently collapses.

A centralized, counter-based architectural scheme.

• Architecture: The Arbiter contains a mathematical binary counter connected to a set of Poll lines that are broadcast to all Masters.
• Mechanism: If the global Bus Request line is asserted, the Arbiter aggressively increments its binary counter (e.g., 000, 001, 010). If the counter outputs 010, Master 2 checks if it requested the bus. If yes, it asserts the Bus Busy line, halting the counter and taking control. If no, the Arbiter increments to 011.
• Merit: Priority is completely programmable. The Arbiter can mathematically reset the counter or start from different numbers, ensuring fair access and zero starvation.
• Demerit: Counting takes multiple clock cycles, making it relatively slow for high-performance systems.

The absolute standard for massive, high-speed multi-core architectures.

• Architecture: Daisy chaining is completely abandoned. Every single Master has its own dedicated, private Bus Request (BR) wire and a dedicated private Bus Grant (BG) wire physically connected directly to the central Arbiter.
• Mechanism: If Masters 2, 5, and 8 request the bus simultaneously, the Arbiter receives all requests instantly. The Arbiter contains a highly complex, lightning-fast hardware priority encoder. It executes a mathematical algorithm (e.g., Round Robin or strict Priority) to decide who wins, and asserts the specific BG line for the winner in a single clock cycle.
• Merit: Blisteringly fast. Absolute flexibility in assigning dynamic priorities. A hardware failure in one Master cannot physically cripple the others.
• Demerit: Requires a massive number of physical silicon wires routing across the motherboard, increasing manufacturing cost and complexity.