Q14Computer Architecture and Organization

Instruction Pipelining dramatically increases CPU throughput by overlapping instruction execution. However, this massive speedup is violently interrupted by Data Hazards. A Data Hazard occurs when the mathematical execution of Instruction B is strictly dependent on the unwritten, incomplete result of Instruction A.

The Read-After-Write (RAW) Catastrophe

Consider this strict assembly sequence: 1. ADD R1, R2, R3 (Mathematically calculates $R1=R2+R3$) 2. SUB R4, R1, R5 (Mathematically calculates $R4=R1-R5$)

In a standard 5-stage pipeline (Fetch, Decode, Execute, Memory, Write-Back), the ADD instruction does not physically write the new value of R1 into the register file until stage 5. However, the SUB instruction needs to read R1 during stage 2. Because the data isn't there yet, the hardware must violently stall the pipeline for 3 clock cycles, destroying performance.

The Architectural Solution: Operand Forwarding (Bypassing)

To solve this, CPU engineers invented Operand Forwarding. The hardware architecture is violently modified to include massive internal data bypass wires.

• The ALU actually finishes calculating the new value of R1 at the end of Stage 3 (Execute).
• Instead of waiting for Stage 5 to write it to the register, the internal hardware immediately physically "forwards" the electrical voltage from the output of the ALU directly back to the input of the ALU for the very next clock cycle.
• The SUB instruction receives the correct, calculated data instantly without a single clock cycle of stalling. The mathematical conflict is completely eradicated in hardware.