Q17Computer Architecture and Organization

Representing integers in binary is trivial. Representing massive fractional numbers (like $6.022\times 10^{23}$) requires a highly complex mathematical architecture. The IEEE 754 standard is the absolute universal hardware protocol for floating-point arithmetic across all modern CPUs and GPUs.

The 32-Bit Single Precision Architecture

The standard violently slices a 32-bit register into three strict mathematical fields:

• 1. Sign Bit (1 bit): Bit 31. 0 mathematically dictates a positive number; 1 dictates negative.
• 2. Exponent (8 bits): Bits 30-23. Instead of standard two's complement, it uses an "Excess-127" biased format. The true mathematical exponent $E$ is calculated by subtracting 127 from the stored binary integer. This allows the representation of both massive positive and tiny negative exponents.
• 3. Mantissa / Fraction (23 bits): Bits 22-0. It strictly utilizes a "Hidden Bit" architecture. The number is mathematically normalized so that the first bit is always a 1 (e.g., $1.xxxxx$). Because it is always a 1, the hardware physically does not store it, magically providing 24 bits of mathematical precision inside 23 physical bits.

The Mathematical Equation

The exact decimal value $V$ is calculated by the hardware using this strict formula:

$$V=(-1{)}^{\text{Sign}}\times (1+\text{Mantissa})\times 2^{(\text{Exponent}-127)}$$

IEEE 754 also mathematically reserves specific binary patterns to represent Infinity ($+\infty$, $-\infty$) and NaN (Not a Number) to handle catastrophic divide-by-zero errors safely.