RTUEE / EC / EEEYr 2021 · Sem 7

VHDL

10 questions

Q116 marks

Q.1. Explain the following terms in VHDL - [4x4=16]

  • (a) Functional Simulation [4]
  • (b) Timing Simulation [4]
  • (c) Design Flow [4]
  • (d) Design Methodology [4]
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Q216 marks

Q.1. Write VHDL code for - [4x4=16]

  • (a) Full Adder [4]
  • (b) 2x1 MUX [4]
  • (c) 3-input NOR gate [4]
  • (d) SR-Latch [4]
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Q316 marks

Q.2. How the following is defined/written in VHDL - [4x4=16]

  • (a) Event-driven Simulation [4]
  • (b) Data Types [4]
  • (c) Signals Verses Variables [4]
  • (d) Packages [4]

Explain with an example.

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Q416 marks

Q.2. (a) Write VHDL code for a 4-bit down counter using sequential statements. [8]

(b) Define elaboration, signal driver using an example. [8]

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Q516 marks

Q.3. (a) Write VHDL code for a 4-bit shift register. [8]

(b) Write VHDL code for a code converter (Consider any one example). [8]

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Q616 marks

Q.3. (a) Write VHDL code for JK flip-flop in two styles. [8]

(b) Write a VHDL code for 7-segment to BCD code converter using select signal assignment. [8]

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Q716 marks

Q.4. (a) Write a VHDL code for a Moore m/c and explain the general procedure for such a m/c. [8]

(b) Identify shift register as Moore or Mealy m/c and write its VHDL code accordingly. [8]

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Q816 marks

Q.4. Write a VHDL code for a Vending Machine that delivers tea at a cost of Rs 5 and accepts coins of Rs 1, Rs 2 and Rs 5. [16]

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Q916 marks

Q.5. (a) How memory organization is defined in VHDL? Write a VHDL code to organize 10k (SRAM) memory. [8]

(b) Explain the clock synchronization in VHDL. [8]

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Q1016 marks

Q.5. (a) Design a 4-bit divider and draw its flow diagram. Then write the VHDL code for it. [10]

(b) Explain shifting & sorting operation in VHDL. [6]

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