Q6VHDL

(a) JK Flip-Flop in Two Styles

-- Style 1: Behavioral (process-based)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity jk_ff_behavioral is
    port (
        clk, J, K : in  STD_LOGIC;
        Q         : out STD_LOGIC
    );
end jk_ff_behavioral;

architecture behavioral of jk_ff_behavioral is
    signal Q_int : STD_LOGIC := '0';
begin
    process(clk)
    begin
        if rising_edge(clk) then
            case (J & K) is
                when "00" => Q_int <= Q_int;
                when "01" => Q_int <= '0';
                when "10" => Q_int <= '1';
                when "11" => Q_int <= not Q_int;
                when others => Q_int <= 'X';
            end case;
        end if;
    end process;
    Q <= Q_int;
end behavioral;

-- Style 2: Dataflow (using the JK characteristic equation)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity jk_ff_dataflow is
    port (
        clk, J, K : in  STD_LOGIC;
        Q         : out STD_LOGIC
    );
end jk_ff_dataflow;

architecture dataflow of jk_ff_dataflow is
    signal Q_int : STD_LOGIC := '0';
begin
    process(clk)
    begin
        if rising_edge(clk) then
            Q_int <= (J and not Q_int) or (not K and Q_int);
        end if;
    end process;
    Q <= Q_int;
end dataflow;

The first style uses a behavioral, case-statement-based description directly listing the four possible J,K input combinations and their corresponding next-state behavior (no change, reset to 0, set to 1, and toggle for J=K='1'), closely mirroring the JK flip-flop's classical truth table as typically taught in digital logic courses, making it very readable and directly traceable to the standard JK excitation table. The second style instead implements the JK flip-flop's characteristic equation directly, Q(next) = JQ'(current) + K'Q(current), a single Boolean expression algebraically derived from the same truth table but expressed as one combinational equation evaluated within the clocked process - both styles are logically equivalent and synthesize to the same underlying edge-triggered flip-flop hardware, illustrating that VHDL, like other hardware description languages, allows the same digital logic function to be expressed through multiple different but equally valid coding styles.

(b) 7-Segment to BCD Code Converter Using Select Signal Assignment

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity seg7_to_bcd is
    port (
        seg : in  STD_LOGIC_VECTOR(6 downto 0);  -- a,b,c,d,e,f,g
        bcd : out STD_LOGIC_VECTOR(3 downto 0)
    );
end seg7_to_bcd;

architecture dataflow of seg7_to_bcd is
begin
    with seg select
        bcd <= "0000" when "1111110",  -- 0
               "0001" when "0110000",  -- 1
               "0010" when "1101101",  -- 2
               "0011" when "1111001",  -- 3
               "0100" when "0110011",  -- 4
               "0101" when "1011011",  -- 5
               "0110" when "1011111",  -- 6
               "0111" when "1110000",  -- 7
               "1000" when "1111111",  -- 8
               "1001" when "1111011",  -- 9
               "XXXX" when others;
end dataflow;

This code converter takes a 7-bit input representing which of the seven segments (a through g) of a 7-segment display are active for a given displayed digit, and produces the corresponding 4-bit BCD (Binary Coded Decimal) code for that digit, using VHDL's selected signal assignment construct ('with...select...when'), which directly and clearly expresses a lookup-table-style mapping from a set of specific input patterns to their corresponding output values, exactly analogous to a case statement but written as a single concurrent (rather than sequential, process-based) statement. The 'when others' clause handles any of the remaining input bit patterns not corresponding to a valid standard digit (invalid or don't-care segment combinations), assigning an 'XXXX' (unknown) output to explicitly flag such inputs as unrecognized rather than silently producing an arbitrary or misleading BCD value.

Both circuits in this question are described using selection-based VHDL constructs that map cleanly to lookup-table style hardware, but at very different scales. The JK flip-flop's case statement inside a clocked process describes a tiny, 4-entry truth table evaluated once per clock edge, synthesizing to only a handful of gates (or directly to a dedicated flip-flop with additional gating logic) since there are only two single-bit inputs; the 7-segment-to-BCD converter's selected signal assignment, by contrast, describes a 10-entry (plus a default 'others' case) lookup table over a 7-bit input, and while it is written in an analogous selection style, it will synthesize to noticeably more combinational logic (effectively a small read-only lookup structure) because of its much larger input space and number of distinct recognized patterns.

The 'when others' catch-all clause in the 7-segment converter is not merely a stylistic nicety but a synthesis requirement in standard VHDL practice: a selected signal assignment (like a case statement) must cover every possible value of the selector expression, and since the 7-bit seg input has 128 possible bit patterns while only 10 of them correspond to valid digit segment patterns, the 'when others' clause is mandatory to make the assignment legal and complete. Assigning "XXXX" for all unrecognized patterns is a deliberate design choice reflecting good defensive coding practice - explicitly flagging invalid or unexpected input combinations with an unmistakable unknown output, rather than allowing the synthesis tool to infer an arbitrary default behavior (such as inferring a latch, or silently mapping unreachable cases to '0000') which could mask a real hardware fault (such as a broken segment) behind a plausible-looking but incorrect BCD output.

It is instructive to verify the two JK flip-flop styles produce identical results by tracing through the toggle case (J=K='1') in both versions: in the behavioral case-statement style, the "11" branch explicitly assigns 'Q_int <= not Q_int', directly stating the toggle behavior; in the characteristic-equation style, substituting J=K='1' into 'Q_int <= (J and not Q_int) or (not K and Q_int)' gives '(1 and not Q_int) or (0 and Q_int)', which simplifies to 'not Q_int or 0', i.e. simply 'not Q_int' - confirming both descriptions produce exactly the same next-state value for this input combination, and similarly substituting each of the other three J,K combinations into the characteristic equation reproduces exactly the same four outcomes listed in the case-statement version, algebraically confirming the equivalence of the two coding styles rather than merely asserting it.

The 7-segment-to-BCD converter's structure also invites a natural comparison with the earlier binary-to-Gray converter examined elsewhere in this paper: whereas the Gray code converter is implemented with a handful of simple per-bit XOR equations because of the regular, easily-expressed mathematical relationship between binary and Gray code, the 7-segment-to-BCD mapping has no such simple closed-form Boolean equation relating input segment pattern to output BCD code, since the assignment of which segments are lit for a given digit is an essentially arbitrary display convention rather than a mathematical transformation - this is precisely why the 7-segment converter must instead be described using an explicit case-by-case lookup table (the selected signal assignment shown here), while the Gray code converter can instead be described far more compactly using direct algebraic XOR equations, illustrating how the most appropriate VHDL coding construct for a given combinational function depends heavily on whether or not that function has an underlying regular mathematical structure that can be expressed algebraically.

It is also worth noting that both sub-parts of this question use the STD_LOGIC_VECTOR / STD_LOGIC types from the std_logic_1164 package rather than plain BIT and BIT_VECTOR, consistent with standard modern VHDL practice discussed elsewhere in this examination, ensuring that the simulator can correctly represent any uninitialized ('U') or unknown ('X') condition on the seg input or the internal flip-flop state, which is particularly relevant to correctly modeling the JK flip-flop's initial power-up state before its first clock edge establishes a known value.

Both circuits also share the property of being purely single-clock-domain designs with no cross-domain signal interaction, meaning neither requires any of the synchronizer techniques discussed in relation to clock synchronization elsewhere in this examination - the JK flip-flop is clocked directly by a single clk input with no external asynchronous inputs beyond J and K (assumed already synchronous to that same clock), and the 7-segment converter is purely combinational with no clock at all, making both straightforward, self-contained examples appropriate for introducing basic sequential and combinational VHDL coding styles before more complex multi-clock-domain designs are introduced.