Q2VHDL

(a) Full Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is
    port (
        A, B, Cin : in  STD_LOGIC;
        Sum, Cout : out STD_LOGIC
    );
end full_adder;

architecture dataflow of full_adder is
begin
    Sum  <= A xor B xor Cin;
    Cout <= (A and B) or (B and Cin) or (A and Cin);
end dataflow;

A full adder takes three single-bit inputs (A, B, and a carry-in Cin) and produces a Sum output and a Cout (carry-out) output, using the standard full-adder equations: Sum is the three-input XOR of A, B, and Cin (giving a 1 output whenever an odd number of the three inputs are 1), and Cout is 1 whenever at least two of the three inputs are 1, expressed as the OR of the three possible pairwise AND combinations. This dataflow-style VHDL code directly implements these two Boolean equations using concurrent signal assignment statements, giving a purely combinational circuit that immediately reflects any change in its inputs at its outputs, with no clock or internal state involved.

(b) 2x1 MUX

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2x1 is
    port (
        I0, I1 : in  STD_LOGIC;
        Sel    : in  STD_LOGIC;
        Y      : out STD_LOGIC
    );
end mux2x1;

architecture dataflow of mux2x1 is
begin
    Y <= I0 when Sel = '0' else I1;
end dataflow;

A 2:1 multiplexer selects one of two input signals (I0 or I1) to route to the single output Y, based on the value of a single select line Sel - when Sel is '0', input I0 is passed to the output; when Sel is '1', input I1 is passed instead. This VHDL code uses a conditional signal assignment ('when...else' construct) directly expressing this selection logic in a single, readable concurrent statement, which synthesizes efficiently to the standard 2:1 multiplexer gate-level structure (typically implemented as two AND gates, one OR gate, and one inverter, or directly as a dedicated multiplexer primitive in the target technology library).

(c) 3-input NOR gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity nor3 is
    port (
        A, B, C : in  STD_LOGIC;
        Y       : out STD_LOGIC
    );
end nor3;

architecture dataflow of nor3 is
begin
    Y <= A nor B nor C;
end dataflow;

A 3-input NOR gate produces a logic-1 output only when all three inputs A, B, and C are simultaneously 0; if any one or more of the inputs is 1, the output is 0. VHDL's 'nor' operator, applied directly across all three input signals in a single concurrent statement, directly and unambiguously expresses this multi-input NOR function, and standard synthesis tools map this directly to a single 3-input NOR gate primitive (or an equivalent structure) in the target technology library, without requiring the designer to manually decompose it into a combination of simpler 2-input gates.

(d) SR-Latch

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sr_latch is
    port (
        S, R : in  STD_LOGIC;
        Q, Qn : out STD_LOGIC
    );
end sr_latch;

architecture structural of sr_latch is
    signal Q_int, Qn_int : STD_LOGIC;
begin
    Q_int  <= S nor Qn_int;
    Qn_int <= R nor Q_int;
    Q  <= Q_int;
    Qn <= Qn_int;
end structural;

An SR (Set-Reset) latch is the most basic sequential memory element, built from two cross-coupled NOR gates whose outputs feed back into each other's inputs, creating a bistable circuit that holds (latches) its state indefinitely as long as both S and R remain 0. Setting S=1 (with R=0) forces Q to 1 (the 'set' condition); setting R=1 (with S=0) forces Q to 0 (the 'reset' condition); and S=R=0 holds the previously latched state. This VHDL code models the cross-coupled feedback structure directly using two concurrent NOR signal assignments referencing each other's internal signals (Q_int and Qn_int), correctly capturing the essential feedback-loop behavior that makes an SR latch fundamentally different from a purely combinational circuit, since its output depends on its own previous state rather than being a pure function of only its current inputs (the S=R=1 condition is conventionally treated as invalid/not used, since it would force both outputs to 0 simultaneously, violating the expected complementary Q/Qn relationship).

All four of these circuits are purely combinational (the full adder, the 2x1 MUX, and the 3-input NOR gate) or, in the case of the SR-latch, level-sensitive sequential, and none of them involve a clock signal, which distinguishes them from the clocked, edge-triggered sequential circuits (flip-flops, counters, shift registers) examined elsewhere in this question paper. Because the full adder, MUX, and NOR gate are described using purely concurrent signal assignments with no process or clock, each output is recomputed immediately whenever any relevant input changes, which is precisely the intended semantics for combinational logic and also the reason these three circuits require no reset signal or initial-value handling: a combinational circuit's output is always simply a function of its present inputs, with no stored state to initialize.

The SR-latch is the one exception among these four sub-circuits, since its cross-coupled NOR structure introduces feedback and therefore genuine sequential (memory) behavior, even though it is still not clocked. This makes the SR-latch's VHDL description subtly different in character from the others: although it is still written using only concurrent signal assignments (no process block), the two assignments reference each other's signals, so the simulator's event-driven engine must iterate the two NOR expressions across successive delta-cycles within the same simulation time-step until the internal signals converge to a stable resolved value, illustrating how even a purely concurrent VHDL description can model feedback-based sequential behavior without needing an explicit clocked process, provided the designer understands that this converges through simulation delta-delays rather than through any explicit clocking mechanism.

It is also useful to note that all four sub-circuits in this question use the STD_LOGIC type from the IEEE std_logic_1164 package rather than the native VHDL BIT type, following the standard convention (discussed further elsewhere in this examination) of using the richer nine-valued STD_LOGIC type for any signal intended to realistically represent a hardware wire, since this allows the simulator to correctly represent uninitialized ('U') or unknown ('X') conditions on these signals during simulation, which is particularly relevant for the SR-latch's internal feedback signals Q_int and Qn_int, whose initial simulated value before the first stable state is established would otherwise be ambiguous under the simpler BIT type.

Finally, it is worth noting that all four circuits share the same basic VHDL source structure - a library/use clause bringing in std_logic_1164, an entity declaration listing ports, and an architecture body providing the implementation - which is the minimum skeleton every synthesizable VHDL design unit requires, regardless of whether the underlying logic is combinational (as in the adder, MUX, and NOR gate) or feedback-based sequential (as in the latch).

This consistent skeleton is a deliberate feature of the language: because every entity/architecture pair follows the same declaration pattern, a reader familiar with VHDL syntax can quickly locate the port interface (in the entity) and the actual logic (in the architecture) of any unfamiliar design, which is part of why VHDL, despite its verbosity, remains readable and maintainable across large multi-engineer design projects.

Each of these four designs was also written using the 'dataflow' or 'structural' architecture naming convention to clearly signal its coding style to any later reader, an informal but widely followed VHDL naming practice that helps a design team quickly identify, at a glance across a large project's source files, which architectures are simple concurrent dataflow descriptions versus which involve explicit structural component interconnection, without needing to open and read the full body of every architecture just to determine its underlying coding style.