Q5VHDL

(a) 4-bit Shift Register

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shift_reg4 is
    port (
        clk, reset, serial_in : in  STD_LOGIC;
        parallel_out          : out STD_LOGIC_VECTOR(3 downto 0)
    );
end shift_reg4;

architecture behavioral of shift_reg4 is
    signal reg : STD_LOGIC_VECTOR(3 downto 0);
begin
    process(clk, reset)
    begin
        if reset = '1' then
            reg <= "0000";
        elsif rising_edge(clk) then
            reg <= reg(2 downto 0) & serial_in;
        end if;
    end process;
    parallel_out <= reg;
end behavioral;

This 4-bit serial-in, parallel-out shift register shifts a new serial_in bit into the least significant bit position on every clock edge, with all existing bits shifting one position toward the most significant bit, implemented concisely using the VHDL concatenation operator '&': the expression 'reg(2 downto 0) & serial_in' takes the lower three bits of the current register value and appends the new incoming serial_in bit after them, producing the new 4-bit register value with the correct shifted arrangement. This shift-register structure is a fundamental building block for serial-to-parallel data conversion, delay lines, and, as examined elsewhere in this examination, can itself be recognized and modeled as either a Moore or Mealy finite state machine depending on how its output is defined relative to its internal state.

(b) Code Converter - Binary to Gray Code (4-bit example)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bin2gray is
    port (
        bin  : in  STD_LOGIC_VECTOR(3 downto 0);
        gray : out STD_LOGIC_VECTOR(3 downto 0)
    );
end bin2gray;

architecture dataflow of bin2gray is
begin
    gray(3) <= bin(3);
    gray(2) <= bin(3) xor bin(2);
    gray(1) <= bin(2) xor bin(1);
    gray(0) <= bin(1) xor bin(0);
end dataflow;

This code converter transforms a 4-bit standard binary number into its equivalent 4-bit Gray code representation, using the standard binary-to-Gray conversion rule: the most significant Gray bit equals the most significant binary bit unchanged, and each subsequent (lower) Gray bit is the XOR of that same-position binary bit and the next-higher binary bit. Gray code has the important property that any two numerically adjacent values differ in exactly one bit position, a property exploited in applications such as rotary position encoders and certain low-power counter designs, where minimizing the number of simultaneously switching bits between consecutive states reduces glitches and power consumption compared to standard binary counting.

Both circuits in this question are combinational or clocked in different ways worth contrasting directly. The shift register is fundamentally sequential, since its output depends on previously clocked-in bits held in the internal register 'reg', requiring a clocked process with rising_edge detection; the binary-to-Gray converter, by contrast, is purely combinational, with each Gray output bit expressed as a simple concurrent XOR of two binary input bits, requiring no process, clock, or internal state whatsoever, since a Gray-coded output always corresponds to exactly one binary input with no dependency on any previous input history. This pairing in a single question usefully illustrates the two fundamentally different categories of digital circuit that VHDL must describe using correspondingly different coding styles: process-based sequential descriptions with clocked state elements for anything requiring memory, and concurrent signal assignments for anything that is a pure, instantaneous function of its current inputs.

Extending the shift register beyond 4 bits, or the code converter beyond 4 bits, is straightforward in VHDL because both are written using generically-scalable patterns: the shift register's concatenation-based shifting expression and the converter's per-bit XOR pattern both generalize naturally to any vector width simply by changing the declared vector size, and in a more general-purpose design such widening would typically be expressed using a generic parameter (an entity-level constant such as 'generic (WIDTH : integer := 4)') combined with a for-generate loop to produce the repetitive XOR equations for an arbitrary width, rather than hand-writing each bit's equation individually as done here for the specific 4-bit case - this generic, parameterizable coding style is standard practice for reusable VHDL library components intended to support multiple different data widths from a single source-code description.

A closer look at the shift register's clocked process also reveals an instructive detail about VHDL's asynchronous reset priority: because the process sensitivity list includes both clk and reset, and the if-elsif structure checks reset first, an asserted reset signal takes effect immediately, overriding any pending clock edge, and this priority ordering (reset checked before the clock condition) is what gives this reset its asynchronous character - had the designer instead wanted a synchronous reset, the check for reset would need to be nested inside the 'elsif rising_edge(clk)' branch rather than appearing as a separate, higher-priority condition, exactly as discussed for the down counter examined elsewhere in this paper, reinforcing that the specific placement of the reset condition within the if-elsif chain, not merely the presence of a reset signal, is what determines synchronous versus asynchronous reset behavior in synthesizable VHDL.

The binary-to-Gray converter's four XOR/pass-through equations can also be understood from a hardware-efficiency perspective: because each output bit depends on at most two adjacent input bits, the entire 4-bit conversion requires only three 2-input XOR gates (bit 3 simply passes through unchanged), giving this code converter an extremely small, single-level combinational implementation with minimal propagation delay - this efficiency is a direct consequence of the mathematical structure of the binary-to-Gray mapping itself (each Gray bit only ever depends on the corresponding and next-higher binary bit), and is part of why Gray code conversion is implemented directly in hardware wherever needed (such as ahead of a rotary encoder's output stage) rather than through a slower table-lookup or software-computed approach.

It is also worth comparing the reset styles used across these two sub-circuits: the shift register uses an asynchronous reset (checked ahead of the clock condition in the process), immediately clearing all four stored bits the instant reset is asserted, which is appropriate for a register holding transient shifted data with no requirement to survive exactly one more clock edge before clearing; the Gray code converter, being purely combinational, has no reset at all, since a combinational circuit's output is always simply and immediately recomputed from its current inputs and there is no stored state that could ever need clearing in the first place.

Both circuits also illustrate VHDL's preference for structural, index-based bit manipulation (via slicing, such as reg(2 downto 0), and concatenation, via the '&' operator) over any form of arithmetic looping to describe fixed, small-width bit-level operations, since a fixed 4-bit shift or a fixed 4-bit code conversion is more directly and unambiguously expressed with explicit bit indices than with a generic loop construct, which would typically only be preferred once the design is parameterized to an arbitrary, generic bit-width rather than a single fixed 4-bit case as shown here.

Both circuits are also small enough to verify completely by hand simulation before ever running an actual VHDL simulator: the shift register's behavior for any given sequence of serial_in bits can be traced cycle-by-cycle by hand, and the Gray converter's four output equations can be evaluated directly for all sixteen possible 4-bit binary inputs, making this pair of circuits a good self-check exercise for confirming basic understanding of concatenation-based shifting and per-bit XOR-based code conversion before tackling the larger, more complex sequential designs found elsewhere in this examination.