Q7VHDL

(a) Moore Machine and General Procedure

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity moore_example is
    port (
        clk, reset, x : in  STD_LOGIC;
        y             : out STD_LOGIC
    );
end moore_example;

architecture behavioral of moore_example is
    type state_type is (S0, S1, S2);
    signal current_state, next_state : state_type;
begin
    -- state register process
    process(clk, reset)
    begin
        if reset = '1' then
            current_state <= S0;
        elsif rising_edge(clk) then
            current_state <= next_state;
        end if;
    end process;

    -- next-state logic (combinational)
    process(current_state, x)
    begin
        case current_state is
            when S0 => if x = '1' then next_state <= S1; else next_state <= S0; end if;
            when S1 => if x = '1' then next_state <= S2; else next_state <= S0; end if;
            when S2 => if x = '1' then next_state <= S2; else next_state <= S0; end if;
        end case;
    end process;

    -- output logic depends ONLY on current_state (Moore)
    y <= '1' when current_state = S2 else '0';
end behavioral;

A Moore machine is a finite state machine whose output depends only on the current state, not directly on the current inputs - the output changes only when the state itself changes (typically on a clock edge), giving Moore machine outputs a clean, glitch-free timing relationship to the clock, since the output cannot change asynchronously in the middle of a clock cycle in response to an input transition. The general procedure for designing a Moore machine in VHDL involves three key steps, reflected in the three-part code structure above: first, declare an enumerated state_type and two state signals (current_state and next_state); second, write a clocked process that updates current_state to next_state on each clock edge (with asynchronous reset handling); third, write a separate combinational process (or concurrent statement) that computes next_state as a function of current_state and the inputs, implementing the state transition table; and finally, define the output(s) as a function of current_state alone (never of the inputs directly), which is precisely what distinguishes the Moore machine's output-generation logic from a Mealy machine's, as examined further in relation to the following question of this examination.

(b) Shift Register as Moore or Mealy Machine

A shift register (such as the 4-bit shift register examined in Unit III of this examination) is properly classified as a Moore machine, since its output (the current register contents, or the parallel output bits) depends entirely on its own internal state (the currently stored bit values) and does not depend directly and combinationally on the current serial input value at the same instant - the serial input only affects the register's contents after being clocked in on the next active clock edge, meaning the output observed at any given clock cycle reflects only the state established by previous clock edges, exactly matching the Moore machine's defining characteristic that output is a pure function of state alone.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shift_reg_moore is
    port (
        clk, reset, serial_in : in  STD_LOGIC;
        parallel_out          : out STD_LOGIC_VECTOR(3 downto 0)
    );
end shift_reg_moore;

architecture behavioral of shift_reg_moore is
    signal state : STD_LOGIC_VECTOR(3 downto 0);
begin
    process(clk, reset)
    begin
        if reset = '1' then
            state <= "0000";
        elsif rising_edge(clk) then
            state <= state(2 downto 0) & serial_in;
        end if;
    end process;
    -- Moore-style output: depends only on the state register, not directly on serial_in
    parallel_out <= state;
end behavioral;

This VHDL code is written to explicitly emphasize the Moore classification: the internal register itself is named 'state' (rather than simply a data register) to highlight that it plays the same role as the state variable in a general Moore machine, and the output assignment 'parallel_out <= state' shows the output depending purely and directly on this state signal, with the serial_in input affecting only the next-state computation (inside the clocked process) rather than appearing anywhere in the output assignment itself, consistent with the Moore machine's output = f(state) rule and distinct from how a Mealy machine's output would instead be expressed as output = f(state, input).

It is worth relating the general three-process (or, as coded here, effectively two-process-plus-concurrent-output) Moore machine template to why this specific structural separation is preferred in practice. Splitting the state register into its own clocked process, separate from the purely combinational next-state logic process, makes the design's synchronous elements explicit and unambiguous to both the reader and the synthesis tool: the clocked process contains only the rising_edge-triggered state update (and asynchronous reset), guaranteeing it synthesizes to nothing but flip-flops, while the next-state process, sensitive only to current_state and the inputs (never to the clock), is guaranteed to synthesize to purely combinational logic feeding those flip-flops' data inputs. Combining both the state update and the next-state computation into a single process is also possible and common, but keeping them separate, as done here, is widely regarded as clearer for larger, more complex state machines with many states and transition conditions.

The output logic line 'y <= '1' when current_state = S2 else '0';' is written as a simple concurrent signal assignment entirely outside any process, which is both idiomatic and directly reflects the Moore machine's defining property: because the output depends only on current_state and never on any input signal, it can be expressed as an ordinary combinational concurrent statement rather than needing to live inside the input-sensitive next-state process. This structural placement is itself a useful way to visually and mechanically verify Moore-versus-Mealy classification when reading unfamiliar VHDL code: if the output-generating statement's expression references only state signals, the design is Moore-style, whereas if the same statement (or an equivalent process) also references one or more input signals directly, the design must be Mealy-style instead.

The general Moore-machine procedure described here can also be directly cross-checked against the specific sequence-detector Moore machine examined in the alternate 2019 paper of this same examination, which follows exactly the same three-part template: a clocked state-register process with asynchronous reset to an initial state, a separate combinational next-state process driven by a case statement over the current state and inputs, and a final output expression depending only on the current state. Seeing the identical structural template applied consistently across two different concrete examples (the generic three-state machine shown here, and the four-state '101' sequence detector elsewhere in this paper) reinforces that this is a genuinely general, reusable coding pattern for any Moore machine design, rather than a technique specific to any one particular problem, and recognizing this common template is often the fastest way to correctly structure a new, unfamiliar Moore-machine design from scratch in an examination setting.

It is also worth noting a subtlety in how the shift register's Moore classification generalizes: while the parallel output of the shift register examined here depends only on the current register state, if the design were instead modified so that its output combined the register contents with the current serial_in bit in the very same output equation (for example, computing some function of both the stored bits and the incoming bit without waiting for the next clock edge), the design would immediately become Mealy-style rather than Moore-style, regardless of how the internal register itself is clocked - this shows that the Moore/Mealy classification is determined entirely by how the output signal is computed, not by whether the circuit contains clocked state elements at all, since virtually every non-trivial sequential circuit contains some form of clocked state regardless of its Moore or Mealy output classification.

Finally, both the generic three-state example and the shift-register-as-Moore-machine example in this question use an asynchronous reset to force current_state (or state) back to a known initial value, a coding pattern that is essentially mandatory for any real Moore machine implementation, since without a defined, forced initial state, the state register's value at power-up would be unpredictable ('U' in simulation, and an arbitrary, device-dependent value in real hardware), which could cause the machine to begin operation in an unintended or even physically unreachable state depending on the specific state encoding and transition logic used.