VLSI Design

Q.1. (a) Draw and write the working of enhancement mode PMOS with the help of input-output and transfer characteristics. [8]

(b) Write the names and compare the three technologies used for the fabrication of CMOS transistor. [8]

Q.1. (a) What are the different factors affecting the threshold voltage of MOSFET? Derive the formula used. Also, derive the body effect coefficient. [8]

(b) Draw MOS transistor circuit model and explain the origination of each parameter. [8]

Q.2. (a) Draw voltage transfer characteristics (VTC) of CMOS inverter and derive the expression for Bn/Bp ratio. [8]

(b) Write the names of three types of power dissipation in CMOS logic circuits and derive the expression for total power dissipation. [8]

Q.2. (a) Design the following logic circuits using CMOS logic gate - (i) 3-input NAND gate (ii) S-R Flip-flop [8]

(b) Implement the Boolean expression F=a.(b+b'c') using CMOS logic and also determine the size of each transistor using equivalent inverter transistor sizes. [8]

Q.3. (a) Implement 2x1 multiplexer using transmission gate and draw its layout. [8]

(b) Draw Euler path and layout diagram for 3-input NOR gate and mark all the size/spacing using lambda-rules. [8]

Q.3. (a) What is latch-up problem in CMOS? Draw and explain its physical origin, model and V-I characteristics. [8]

(b) Write the names and explain the techniques used to prevent latch-up problem. [8]

Q.4. (a) Compare NORA and NP (ZIPPER) CMOS logic structures. [8]

(b) Explain various circuit techniques used in domino CMOS circuits for solving charge sharing problem. [8]

Q.4. Draw a circuit diagram of a DRAM cell and explain the following operations - (i) Synchronous read mode (ii) Asynchronous read mode (iii) Leakage currents and refresh operation. [8]

(b) Draw SRAM cell and explain its write and read operation with appropriate timing diagram. [8]

Q.5. (a) Draw VHDL/PLD based ASIC design flow block diagram. Explain each step involved. [8]

(b) Write VHDL code for positive edge triggered S-R flip-flop. [8]

Q.5. (a) Write VHDL code for half adder in structural style. [8]

(b) Write VHDL model for left to right shift register using enable input. [8]