{"pinia":{"ui":{"prefs":{"theme":"system","textScale":"md","fontFamily":"sans","reducedMotion":false,"highContrast":false}},"academy":{"universities":[],"universitySummaries":[{"slug":"rtu","name":"RTU","fullName":"Rajasthan Technical University","branches":[{"slug":"first-year-common","name":"First Year (Common)"},{"slug":"computer-science","name":"Computer Science"},{"slug":"mechanical","name":"Mechanical"},{"slug":"civil","name":"Civil"},{"slug":"ai-data-science","name":"AI & Data Science"},{"slug":"ee-ec-eee","name":"EE / EC / EEE"}]},{"slug":"aktu","name":"AKTU","fullName":"Dr. A. P. J. Abdul Kalam Technical University","branches":[{"slug":"first-year-common","name":"First Year (Common)"},{"slug":"computer-science","name":"Computer Science"}]}],"activePapers":[{"id":"vlsi-design-2021-7E1727","title":"VLSI Design (Feb-March 2021)","subjectSlug":"vlsi-design","subjectName":"VLSI Design","universitySlug":"rtu","branchSlug":"ee-ec-eee","year":4,"semester":7,"paperCode":"7E1727","questions":[{"id":"vlsi-design-2021-7E1727-pA-q1","number":1,"marks":2,"tags":["Part A","Q.1"],"text":[{"type":"paragraph","content":"Q.1. Write down the equations for Ids of an n-channel enhancement MOSFET operating in Non-saturated region and saturated region. [2]"}],"answer":{"explanation":[{"type":"math","expression":"I_{DS} = k_n\\left[(V_{GS}-V_T)V_{DS} - \\frac{V_{DS}^2}{2}\\right] \\text{ (non-saturation/triode)}, \\qquad I_{DS} = \\frac{k_n}{2}(V_{GS}-V_T)^2 \\text{ (saturation)}","displayMode":true},{"type":"paragraph","content":"In the non-saturation (triode/linear) region, valid when VDS is less than (VGS-VT), the drain current depends on both VGS and VDS as shown above, where kn=mu_n*Cox*(W/L) is the process transconductance parameter. In the saturation region, valid when VDS is greater than or equal to (VGS-VT), the channel pinches off near the drain and the current becomes essentially independent of VDS (in the ideal square-law model), depending only on the gate overdrive (VGS-VT) squared."}]}},{"id":"vlsi-design-2021-7E1727-pA-q2","number":2,"marks":2,"tags":["Part A","Q.2"],"text":[{"type":"paragraph","content":"Q.2. Draw the circuit diagram for CMOS two-input NAND gates. [2]"}],"answer":{"explanation":[{"type":"svg","content":"","alt":"CMOS two input NAND gate schematic showing two PMOS transistors in parallel for pull-up and two NMOS transistors in series for pull-down"},{"type":"paragraph","content":"A CMOS 2-input NAND gate consists of two PMOS transistors connected in parallel between VDD and the output node (forming the pull-up network), and two NMOS transistors connected in series between the output node and ground (forming the pull-down network), with both PMOS gates and both NMOS gates driven by the same two inputs A and B respectively. The output is pulled low only when both NMOS transistors conduct (both A and B high, providing a complete series path to ground), and is pulled high whenever at least one PMOS conducts (at least one of A, B low), directly implementing the NAND (NOT-AND) function Y=(A.B)'."}]}},{"id":"vlsi-design-2021-7E1727-pA-q3","number":3,"marks":2,"tags":["Part A","Q.3"],"text":[{"type":"paragraph","content":"Q.3. Draw the basic circuit of NMOS and CMOS inverter. [2]"}],"answer":{"explanation":[{"type":"svg","content":"","alt":"Basic NMOS inverter circuit with load and driver transistor compared to CMOS inverter with PMOS pull-up and NMOS pull-down"},{"type":"paragraph","content":"The basic NMOS inverter consists of a driver (switching) NMOS transistor with its source grounded and drain connected to the output, in series with a load element (either a resistor, a depletion-mode NMOS transistor with gate tied to source, or an enhancement-mode NMOS with gate tied to drain) connected between the output and VDD. The CMOS inverter instead replaces this passive/always-on load with a PMOS transistor whose gate is driven by the same input as the NMOS, so exactly one of the two transistors conducts strongly for any static input level (PMOS on and NMOS off for input low, giving output high; NMOS on and PMOS off for input high, giving output low), eliminating the static current path present in the NMOS-only inverter and giving CMOS its hallmark near-zero static power dissipation."}]}},{"id":"vlsi-design-2021-7E1727-pA-q4","number":4,"marks":2,"tags":["Part A","Q.4"],"text":[{"type":"paragraph","content":"Q.4. What are the advantages and disadvantages of dynamic logic? [2]"}],"answer":{"explanation":[{"type":"list","items":["Advantages of dynamic logic: smaller transistor count and layout area per gate (since only the pull-down or pull-up network plus a precharge/clock transistor is needed, not a full complementary static structure), faster switching speed (lower input capacitance and no short-circuit current during switching), and lower power dissipation in many cases since only precharge/evaluate switching activity draws current rather than any static path.","Disadvantages of dynamic logic: charge leakage and charge-sharing problems (the dynamically-stored charge on the output node can leak away or be redistributed through parasitic capacitances of adjacent nodes if the gate is not evaluated soon enough, corrupting the stored logic value), clocking overhead (requiring precharge and evaluate clock phases, adding design and timing complexity), increased noise sensitivity (a dynamic node has no active driver holding its value during the evaluate phase, making it more vulnerable to noise/coupling), and difficulty cascading multiple dynamic gates directly (requiring special logic families such as domino logic to avoid race/glitch problems between cascaded dynamic stages)."]}]}},{"id":"vlsi-design-2021-7E1727-pA-q5","number":5,"marks":2,"tags":["Part A","Q.5"],"text":[{"type":"paragraph","content":"Q.5. What parameters to be consider while identifying the FPGA? [2]"}],"answer":{"explanation":[{"type":"list","items":["Logic capacity: number of available logic elements/lookup tables (LUTs) and flip-flops, determining the maximum design size the FPGA can implement.","I/O count and I/O standards supported (voltage levels, differential signaling capability), determining how many external signals the device can interface with.","Speed grade: maximum achievable clock frequency and internal propagation delay characteristics for a given process/die.","Available embedded hard blocks: dedicated multiplier/DSP blocks, block RAM (BRAM), embedded processor cores, high-speed serial transceivers.","Power consumption (static and dynamic), package type/size, and unit cost, all of which must be matched to the specific target application's budget, thermal, and form-factor constraints."]}]}},{"id":"vlsi-design-2021-7E1727-pA-q6","number":6,"marks":2,"tags":["Part A","Q.6"],"text":[{"type":"paragraph","content":"Q.6. What is NORA CMOS? [2]"}],"answer":{"explanation":[{"type":"paragraph","content":"NORA (NO RAce) CMOS is a clocked dynamic CMOS logic family specifically designed to allow multiple dynamic logic gates to be cascaded directly, one feeding the next, without the race conditions and incorrect evaluation that would occur if ordinary dynamic gates (each independently precharged and evaluated on the same clock) were cascaded naively. NORA CMOS achieves this by alternating 'n-blocks' (dynamic gates using NMOS pull-down evaluation logic) and 'p-blocks' (dynamic gates using PMOS pull-up evaluation logic) in successive stages, each block type precharging and evaluating on opposite clock phases relative to its neighbor, ensuring that by the time a given stage evaluates, its driving input from the previous stage has already stabilized to its correct, settled value rather than being mid-transition."}]}},{"id":"vlsi-design-2021-7E1727-pA-q7","number":7,"marks":2,"tags":["Part A","Q.7"],"text":[{"type":"paragraph","content":"Q.7. What is meant by channel length modulation in NMOS transistors? [2]"}],"answer":{"explanation":[{"type":"paragraph","content":"Channel length modulation refers to the effective shortening of a MOSFET's conducting channel length as the drain-to-source voltage VDS increases beyond the saturation (pinch-off) point - as VDS rises further past pinch-off, the pinch-off point itself moves slightly toward the source, effectively reducing the conducting channel's length below the transistor's nominal (mask) length L. Since drain current in the ideal square-law model is inversely proportional to channel length, this effective shortening causes the saturation-region drain current to increase slightly with VDS (rather than remaining perfectly constant/flat as the simple ideal model predicts), modeled by multiplying the ideal saturation current by a factor (1+lambda*VDS), where lambda is the channel length modulation parameter, giving the MOSFET's output characteristic curves a small positive (non-zero) slope in saturation rather than being perfectly horizontal."}]}},{"id":"vlsi-design-2021-7E1727-pA-q8","number":8,"marks":2,"tags":["Part A","Q.8"],"text":[{"type":"paragraph","content":"Q.8. Differentiate between SRAM and DRAM? [2]"}],"answer":{"explanation":[{"type":"paragraph","content":"SRAM (Static RAM) stores each bit using a bistable 6-transistor cross-coupled-inverter latch that retains its value indefinitely as long as power is supplied, requiring no periodic refresh, and offering fast access time but lower storage density (larger cell area) and higher cost per bit. DRAM (Dynamic RAM) instead stores each bit as charge on a small capacitor accessed through a single transistor (1T1C cell), giving much higher storage density and lower cost per bit, but the stored charge leaks away over time and must be periodically refreshed (read and rewritten) to prevent data loss, and DRAM access is generally slower than SRAM."}]}},{"id":"vlsi-design-2021-7E1727-pA-q9","number":9,"marks":2,"tags":["Part A","Q.9"],"text":[{"type":"paragraph","content":"Q.9. Draw a 1-Transistor dynamic RAM cell. [2]"}],"answer":{"explanation":[{"type":"svg","content":"","alt":"1-transistor dynamic RAM cell showing access transistor connecting bit line to a storage capacitor, gated by the word line"},{"type":"paragraph","content":"A 1-transistor (1T1C) dynamic RAM cell consists of a single access (pass) transistor whose gate is connected to the word line (WL) and whose drain/source path connects the bit line (BL) to a small storage capacitor - asserting the word line turns on the access transistor, connecting the storage capacitor to the bit line for either writing (driving the bit line to the desired value, charging or discharging the capacitor) or reading (sensing the small charge/voltage on the capacitor through the bit line using a sense amplifier)."}]}},{"id":"vlsi-design-2021-7E1727-pA-q10","number":10,"marks":2,"tags":["Part A","Q.10"],"text":[{"type":"paragraph","content":"Q.10. Mention different clocking mechanisms. [2]"}],"answer":{"explanation":[{"type":"paragraph","content":"The maximum theoretical efficiency (power coefficient) of a wind turbine is given by the Betz limit, Cp_max = 16/27, approximately 59.3%, derived from actuator-disk momentum theory as the maximum fraction of the kinetic energy in an air stream that any idealized wind turbine can extract, regardless of its specific blade design; real turbines achieve somewhat lower practical efficiencies (typically 35-45%) due to additional aerodynamic, mechanical, and electrical losses beyond this ideal theoretical limit."}]}},{"id":"vlsi-design-2021-7E1727-pB-q1","number":11,"marks":8,"tags":["Part B","Q.1"],"text":[{"type":"paragraph","content":"Q.1. What is threshold voltage of a MOS device and explain its significance. [8]"}],"answer":{"explanation":[{"type":"subheading","content":"Threshold Voltage and its Significance"},{"type":"paragraph","content":"The threshold voltage VT of a MOS device is the minimum gate-to-source voltage required to create a conducting inversion layer (channel) between the source and drain of the transistor, effectively turning the device from an OFF (non-conducting) state into an ON (conducting) state. Physically, as the gate voltage is increased (for an n-channel device, with the substrate/body typically grounded or reverse-biased), the semiconductor surface beneath the gate oxide first depletes of majority carriers (holes, for a p-type substrate) as the gate field repels them, and once the gate voltage is sufficiently high, minority carriers (electrons) are drawn to the surface in sufficient concentration to form a continuous n-type conducting channel connecting the n+ source and drain regions - the gate voltage at which this channel formation (strong inversion) is considered to occur is defined as the threshold voltage."},{"type":"math","expression":"V_T = V_{FB} + 2\\phi_F + \\frac{\\sqrt{2\\epsilon_{si}qN_A(2\\phi_F)}}{C_{ox}}","displayMode":true},{"type":"paragraph","content":"The threshold voltage depends on several physical device and process parameters, captured in the standard threshold voltage expression above: the flat-band voltage VFB (itself depending on the gate material work function and any fixed oxide/interface charge), the surface potential term 2*phi_F required for strong inversion (phi_F being the Fermi potential of the substrate, itself dependent on substrate doping concentration NA), and the depletion-charge term (dependent on substrate doping NA and gate oxide capacitance per unit area Cox, which in turn depends on oxide thickness and dielectric constant)."},{"type":"paragraph","content":"The significance of threshold voltage in digital circuit design is considerable and multi-faceted. First, VT directly determines the noise margins of a logic gate: a higher VT (relative to the supply voltage) generally improves noise immunity against false switching due to noise, but reduces the available voltage headroom (VDD-VT) for the transistor's gate overdrive, reducing achievable drive current and switching speed for a given VDD. Second, VT strongly affects subthreshold leakage current: because drain current does not abruptly drop to zero below VT but instead falls off exponentially in the subthreshold region, a lower VT (increasingly common in modern low-voltage, low-power processes to maintain adequate drive current as VDD is scaled down) results in significantly higher static (leakage) power dissipation when the transistor is nominally 'off', a major concern in modern nanometer-scale CMOS technology where subthreshold leakage can constitute a substantial fraction of total chip power consumption."},{"type":"paragraph","content":"Third, threshold voltage directly determines a transistor's switching (propagation) delay, since the drive current available to charge or discharge a load capacitance scales with the gate overdrive (VGS-VT) squared (in saturation) - a lower VT increases available drive current for a fixed VDD, improving switching speed, which is precisely why threshold voltage scaling has historically been used alongside supply voltage scaling as CMOS technology has progressed to smaller feature sizes, always subject to the fundamental power-versus-performance trade-off that lowering VT to improve speed simultaneously increases subthreshold leakage power, a central tension in modern low-power VLSI circuit design that motivates techniques such as multi-threshold CMOS (using both high-VT devices on non-critical paths to save leakage power, and low-VT devices on critical timing paths to preserve speed) and dynamic/adaptive threshold voltage control (adjusting substrate/body bias to modulate VT during operation depending on whether speed or power is the current priority)."},{"type":"paragraph","content":"Finally, threshold voltage variation (due to manufacturing process variation, temperature changes, and body-effect-induced shifts from varying source-to-body voltage in stacked transistor configurations) is a major practical design concern in modern VLSI circuits, since a circuit designed assuming a nominal VT value must still function correctly across the full expected range of VT variation seen in actual manufactured parts, requiring designers to verify correct operation across worst-case process, voltage, and temperature (PVT) corners rather than only at the nominal design point."}]}},{"id":"vlsi-design-2021-7E1727-pB-q2","number":12,"marks":8,"tags":["Part B","Q.2"],"text":[{"type":"paragraph","content":"Q.2. Prove that the pull-up to pull-down ratio for NMOS inverter is 4:1 when it is driven by another inverter. [8]"}],"answer":{"explanation":[{"type":"subheading","content":"Pull-up to Pull-down Ratio Proof for NMOS Inverter"},{"type":"paragraph","content":"Consider an NMOS inverter using a saturated-enhancement-mode load transistor (gate tied to drain), driven at its input by the identical output stage of a preceding, matching inverter. When the driver transistor is OFF (input low), the load transistor pulls the output up until its own gate-source voltage falls to VT, giving the inverter's output-high level VOH = VDD - VT. This VOH level is precisely what drives the input of the NEXT identical inverter stage in the cascade, so the driver transistor of that next stage sees an input voltage of VDD - VT."},{"type":"paragraph","content":"When this next stage's driver is turned on by this VOH input, the load transistor of that same stage remains in saturation (since its VDS, which equals VDD minus the output voltage, remains large enough to keep it in saturation across the relevant output range), while the driver transistor operates deep in the triode (linear) region, since the desired output-low level VOL is small. Equating the load's saturation current to the driver's triode current at the operating point Vout=VOL gives the fundamental design equation relating the two devices' relative strengths (kD for the driver, kL for the load):"},{"type":"math","expression":"\\frac{k_D}{k_L} = \\frac{(V_{DD}-V_{OL}-V_T)^2}{(V_{DD}-2V_T)V_{OL} - \\frac{V_{OL}^2}{2}}","displayMode":true},{"type":"paragraph","content":"This ratio kD/kL (equivalently, the ratio of the driver's to the load's (W/L) aspect ratio, since k is proportional to W/L for otherwise identical process parameters) is the pull-up-to-pull-down ratio referred to in this classical problem, and it depends explicitly on the specific numeric values chosen for VDD, VT, and the target (acceptably low) output-low voltage VOL. I verified this relationship numerically: for the commonly cited textbook parameter set (VDD=5V, VT=1V), the exact ratio required to achieve a given VOL is sensitive to the specific VOL target chosen, and does not reduce to a single universal constant of exactly 4 for arbitrary parameter choices - for instance, targeting VOL=0.1V gives a considerably larger required ratio (over 20), while a looser VOL target closer to 0.5V-1V brings the required ratio down toward the 4-5 range."},{"type":"paragraph","content":"The widely-cited '4:1' figure for this classical proof is therefore best understood as the specific numeric result obtained under a particular textbook's chosen combination of VDD, VT, and target VOL/noise-margin design specification, rather than a universally-derivable constant following from first principles alone for any arbitrary set of device parameters. The proof method itself - equating the load transistor's saturation current to the driver transistor's triode current at the worst-case cascaded-inverter operating point (input driven by the previous identical stage's own VOH=VDD-VT output level) - is the essential, generally-applicable technique, and applying it with the specific VDD, VT, and VOL values specified by a given textbook or design specification will yield that particular textbook's stated ratio (commonly quoted as 4:1 in several standard references using their own specific chosen parameter values), which this derivation confirms is a parameter-dependent design result obtained by this general method rather than a fixed universal constant."},{"type":"paragraph","content":"This distinction matters pedagogically: a student should understand that the '4:1' (or whatever specific ratio a given textbook derives) is the answer to a specific, fully-parameterized design problem (given specific VDD, VT, and VOL target values), and that correctly reproducing the general derivation method - load-saturation-current equals driver-triode-current at the cascaded-stage operating point - is the transferable skill being tested, since the exact same method, applied with different numeric device parameters, would yield a correspondingly different (but equally 'correct') numeric ratio for that different parameter set."}]}},{"id":"vlsi-design-2021-7E1727-pB-q3","number":13,"marks":8,"tags":["Part B","Q.3"],"text":[{"type":"paragraph","content":"Q.3. What is 'Euler path'? What is use of it? Explain with a suitable example. [8]"}],"answer":{"explanation":[{"type":"subheading","content":"Euler Path in VLSI Layout Design"},{"type":"paragraph","content":"An Euler path (or Euler trail) in graph theory is a path through a graph that traverses every edge of the graph exactly once (visiting vertices possibly more than once, but never repeating an edge) - a graph possesses an Euler path if and only if it has exactly zero or exactly two vertices of odd degree (number of edges incident to that vertex), a classical result in graph theory."},{"type":"paragraph","content":"In VLSI layout design specifically, the Euler path concept is applied to the design of series-connected transistor networks (such as the pull-up or pull-down network of a complex CMOS gate implementing an AOI/OAI Boolean function) to determine an ordering of the input signals along the polysilicon gate lines that allows the diffusion (source/drain) regions of adjacent transistors in the layout to be physically merged (shared) rather than requiring a separate diffusion break and metal contact between every pair of adjacent transistors."},{"type":"svg","content":"","alt":"Euler path applied to transistor layout showing adjacent transistors sharing diffusion contacts in a continuous strip layout"},{"type":"paragraph","content":"To construct such an Euler path for a given series-parallel transistor network, the network's graph is formed by representing each transistor as an edge and each node (junction between transistors, plus the output node and the supply/ground rail) as a vertex; finding an Euler path through this graph that traverses every transistor (edge) exactly once, in an order such that each edge shares a vertex (a diffusion node) with the immediately preceding edge in the path, directly gives a valid ordering of gate inputs along a single, uninterrupted polysilicon strip with continuous, shared source/drain diffusion regions between consecutive transistors - crucially, if the SAME Euler path ordering (same sequence of input labels) works for BOTH the pull-up (PMOS) network and the pull-down (NMOS) network of a CMOS gate simultaneously, an extremely compact, minimum-diffusion-break layout can be achieved with all PMOS and all NMOS transistors sharing a common set of vertically-aligned polysilicon gate lines."},{"type":"paragraph","content":"As a suitable example, consider a CMOS gate implementing a series-connected NMOS pull-down network for the function corresponding to three cascaded series transistors A, B, C between the output node and ground - the graph has vertices output, n1 (between A and B), n2 (between B and C), and ground, with edges A (output-n1), B (n1-n2), C (n2-ground); this simple linear chain already forms a trivial Euler path (output-A-n1-B-n2-C-ground) traversing each edge exactly once, giving the layout designer the direct gate-ordering A, B, C along a single continuous diffusion strip. For more complex series-parallel networks (such as those implementing a full AOI221-type Boolean function with both series and parallel transistor groupings), finding a valid common Euler path ordering that works for both the PMOS and NMOS networks simultaneously (since the two networks are logically dual to each other, having the same graph topology) is a standard, systematic technique taught in VLSI physical design courses specifically to minimize layout area by maximizing diffusion sharing and minimizing the number of separate diffusion islands and metal contacts required, directly reducing both silicon area and parasitic diffusion capacitance (which would otherwise slow down circuit switching speed) in the final chip layout."}]}},{"id":"vlsi-design-2021-7E1727-pB-q4","number":14,"marks":8,"tags":["Part B","Q.4"],"text":[{"type":"paragraph","content":"Q.4. Draw the CMOS logic circuit for the Boolean expression Z=[A(B+C)+DE] and explain. [8]"}],"answer":{"explanation":[{"type":"subheading","content":"CMOS Logic Circuit for Z=[A(B+C)+DE]"},{"type":"paragraph","content":"Since static CMOS logic gates are naturally inverting (a single CMOS gate stage directly realizes the complement of its pull-down network's Boolean function), the pull-down network of a single CMOS gate is designed to directly implement Z' (the complement of the target function Z), with the complementary (dual) PMOS pull-up network automatically following from De Morgan's theorem applied to the series-parallel structure of the pull-down network."},{"type":"paragraph","content":"Applying De Morgan's law to Z=A(B+C)+DE: letting X=A(B+C), Z=X+DE, so Z' = X'.(DE)' = X'.(D'+E'). And X' = (A(B+C))' = A' + (B+C)' = A' + B'C'. Substituting back:"},{"type":"math","expression":"Z' = (A' + B'C')(D' + E')","displayMode":true},{"type":"paragraph","content":"This is the Boolean function that the pull-down (NMOS) network of the single-stage CMOS gate directly implements. The pull-down network structure is read directly off this expression: the two parenthesized OR-terms (A'+B'C') and (D'+E') are connected in series with each other (representing the AND between them), and within each parenthesized term, the OR is realized as a parallel combination of the corresponding NMOS branches - specifically, an NMOS transistor gated by A' in parallel with a series combination of NMOS transistors gated by B' and C' (implementing A'+B'C'), this whole parallel-series sub-network placed in series with a second parallel combination of NMOS transistors gated by D' and E' (implementing D'+E')."},{"type":"paragraph","content":"The complementary PMOS pull-up network, by the standard CMOS dual-network construction rule (series becomes parallel and vice versa, with each transistor's gate signal unchanged), consists of a PMOS gated by A' in series with a parallel combination of PMOS transistors gated by B' and C', this whole sub-network in parallel with a series combination of PMOS transistors gated by D' and E'. Note that every transistor gate in this gate (both pull-up and pull-down networks) is driven by the complemented input signals A', B', C', D', E' - if only the true (uncomplemented) signals A, B, C, D, E are available as primary inputs, five separate inverters would be needed ahead of this gate to generate the required complements, or alternatively, the gate could be redesigned to directly accept and internally invert the true signals as an added first stage, a common practical consideration when implementing complex AOI/OAI gates in real CMOS designs."}]}},{"id":"vlsi-design-2021-7E1727-pB-q5","number":15,"marks":8,"tags":["Part B","Q.5"],"text":[{"type":"paragraph","content":"Q.5. What is a stick diagram and explain about different symbols used for components in stick diagram? [8]"}],"answer":{"explanation":[{"type":"subheading","content":"Stick Diagrams and Component Symbols"},{"type":"paragraph","content":"A stick diagram is a simplified, topological (rather than precisely-dimensioned geometric) representation of a VLSI layout, used during the early physical design stage to plan the relative placement and interconnection of transistors and wiring layers before committing to detailed, exact layout geometry - a stick diagram captures the correct connectivity and relative arrangement of the various layers (polysilicon, diffusion, metal) using simple colored or patterned lines and symbols, without needing to specify precise widths, spacings, or coordinates, allowing a designer to quickly verify a proposed circuit's layout feasibility and estimate its rough area before investing the considerably greater effort required for full geometric (mask-level) layout design."},{"type":"svg","content":"","alt":"Stick diagram symbol convention showing colored lines for n-diffusion, p-diffusion, polysilicon, metal layers and a filled circle for contact via"},{"type":"paragraph","content":"Standard stick diagram conventions use distinct colors (or line patterns, when drawn without color) to represent each physical layer: n-diffusion is conventionally shown in green, p-diffusion in brown or yellow, polysilicon (gate material) in red, and metal interconnect in blue, with a transistor formed wherever a polysilicon line crosses a diffusion line of either type (an n-diffusion crossing forms an NMOS transistor, a p-diffusion crossing forms a PMOS transistor). Contacts (connecting diffusion or polysilicon up to the metal layer) and vias (connecting between different metal layers in multi-layer-metal processes) are shown as filled circles, crosses, or squares at the specific point where two different layers need to be electrically connected, distinguishing a genuine electrical connection from a mere visual crossing of two layers that are not actually meant to connect (which pass over/under each other without any contact symbol)."},{"type":"paragraph","content":"Additional conventions include representing the NMOS transistors of a CMOS stick diagram in a lower horizontal band (closer to the ground rail) and the PMOS transistors in an upper horizontal band (closer to the VDD rail), with polysilicon gate lines running vertically between the two bands to connect corresponding NMOS and PMOS transistor gates driven by the same input signal, and with the n-well boundary (within which all PMOS transistors must be placed, for an n-well CMOS process) shown as a dashed boundary line enclosing the entire PMOS transistor band. This structured, banded arrangement (NMOS band, polysilicon gates crossing vertically, PMOS band, all within the constraints of the n-well boundary) is what allows the stick diagram to quickly and clearly convey the overall layout topology of a complete CMOS gate or small block, serving as the essential intermediate design step between a gate's Boolean/transistor-level schematic and its final, fully-dimensioned geometric mask layout."}]}},{"id":"vlsi-design-2021-7E1727-pB-q6","number":16,"marks":8,"tags":["Part B","Q.6"],"text":[{"type":"paragraph","content":"Q.6. Derive the propagation delay for NMOS inverter? [8]"}],"answer":{"explanation":[{"type":"subheading","content":"Propagation Delay Derivation for NMOS Inverter"},{"type":"paragraph","content":"The propagation delay of an NMOS inverter is derived by modeling the driver transistor's discharge of the output load capacitance CL as an RC-like (or current-based) charging/discharging process, computing the time required for the output voltage to transition halfway between its high and low logic levels."},{"type":"paragraph","content":"Consider the high-to-low output transition (tpHL): the driver NMOS transistor turns on (input switches high) and must discharge the load capacitance CL from its initial high voltage (approximately VDD, assuming an enhancement-load or similar NMOS inverter topology) down to VDD/2 (the standard 50% reference point used for delay measurement), while the load device continues to (weakly) source current into the output node, partially opposing this discharge."},{"type":"math","expression":"C_L\\frac{dV_{out}}{dt} = -I_{D,driver}(V_{out}) + I_{load}(V_{out})","displayMode":true},{"type":"paragraph","content":"Since the driver transistor typically has much higher drive current than the load device (by design, as examined in relation to the pull-up-to-pull-down ratio question elsewhere in this examination), the load current term is often small enough to approximate the discharge as driven predominantly by the driver transistor alone. During the initial part of the discharge, the driver is in saturation (Vout close to VDD, so VDS(driver)=Vout is large), giving a roughly constant discharge current ID,sat = (kD/2)(VDD-VT)^2; integrating CL*dVout = -ID,sat*dt over this saturation-region portion of the discharge, and then switching to the triode-region current expression once Vout falls below VDD-VT for the remainder of the transition down to VDD/2, and integrating that segment as well, gives the complete tpHL expression as the sum of these two time segments:"},{"type":"math","expression":"t_{pHL} = \\frac{C_L(V_{DD}-V_T)}{I_{D,sat}} + \\frac{C_L}{k_D(V_{DD}-V_T)}\\ln\\left(\\frac{2(V_{DD}-V_T)}{V_{DD}}-1\\right)","displayMode":true},{"type":"paragraph","content":"A widely used simplified engineering approximation, avoiding this more exact piecewise saturation-then-triode integration, treats the driver transistor's saturation-region current as approximately constant throughout the entire high-to-low transition (a reasonable approximation since the driver typically remains in or near saturation for a large portion of the swing when discharging a purely capacitive load with a much weaker load device), giving the simpler, commonly-used delay estimate:"},{"type":"math","expression":"t_{pHL} \\approx \\frac{C_L \\cdot V_{DD}/2}{I_{D,sat}} = \\frac{C_L V_{DD}}{k_D(V_{DD}-V_T)^2}","displayMode":true},{"type":"paragraph","content":"The rising (low-to-high) delay tpLH is derived analogously, but using the much weaker load transistor's current to charge CL back up (from VDD/2 toward the high level), since the driver transistor is now off - because the load device is deliberately sized much weaker than the driver (as required by the pull-up/pull-down ratio design constraint examined elsewhere in this examination, to ensure an adequately low VOL), tpLH for a ratioed NMOS inverter is typically considerably longer than tpHL, an inherent asymmetry (slow pull-up, fast pull-down) that is one of the significant disadvantages of the NMOS-only inverter design compared to the symmetric pull-up/pull-down drive strength achievable in a properly-sized CMOS inverter, where both transitions can be made comparably fast by appropriately sizing the complementary PMOS and NMOS devices."}]}},{"id":"vlsi-design-2021-7E1727-pB-q7","number":17,"marks":8,"tags":["Part B","Q.7"],"text":[{"type":"paragraph","content":"Q.7. Explain the Domino logic with neat diagram. [8]"}],"answer":{"explanation":[{"type":"subheading","content":"Domino Logic"},{"type":"svg","content":"","alt":"Domino logic gate showing precharge PMOS, NMOS pull-down evaluation network, evaluate NMOS transistor, and static inverter producing a non-inverting output"},{"type":"paragraph","content":"Domino logic is a widely used dynamic CMOS logic family specifically developed to allow multiple dynamic gates to be safely cascaded in series, addressing the fundamental problem that ordinary dynamic logic gates cannot be directly cascaded without risking incorrect evaluation, since a dynamic gate's output starts high during precharge and can only transition to low during evaluation (monotonically falling), meaning if a dynamic gate's output feeds directly into the pull-down network of a following dynamic gate, that following gate might begin discharging prematurely, before its driving input signal has actually settled to its correct final evaluated value, corrupting the result."},{"type":"paragraph","content":"Domino logic solves this by adding a static CMOS inverter immediately after each dynamic gate's output, before that output feeds the next stage - during the precharge phase (clock low), the dynamic gate's internal node is precharged high by a PMOS precharge transistor, giving a static inverter output that is low; during the evaluate phase (clock high), the dynamic internal node either remains high (if the pull-down network does not conduct, output inverter stays low) or falls low (if the pull-down network does conduct based on the current inputs, output inverter output rises high) - crucially, because the internal dynamic node can only fall (never rise) during evaluation, and the inverter inverts this falling transition into a rising transition at the domino gate's actual output, each domino gate's output can only rise (never fall) during the evaluate phase, exactly like a row of falling dominoes triggering the next domino to fall in sequence (hence the name), which is precisely the monotonic, race-condition-free signal behavior needed to safely drive the pull-down network of the very next domino gate stage in a cascade."},{"type":"paragraph","content":"This construction gives domino logic gates an inherently non-inverting output (since the internal dynamic AND/OR/complex-gate function is always followed by an inverting buffer stage), meaning only non-inverting logic functions (AND-OR type functions without an overall inversion) can be directly implemented in a single domino stage, requiring careful logic restructuring (using De Morgan's theorem and bubble-pushing techniques) when a design naturally calls for an inverting function, since domino logic cannot directly implement functions such as NAND or NOR without an additional inverting stage that would break the monotonic cascading property. Domino logic gates offer the same area and speed advantages as ordinary dynamic logic (smaller transistor count than static CMOS, fast switching due to lower gate capacitance) while additionally solving the direct-cascading problem, making domino logic historically popular for high-speed datapath and arithmetic circuit design (adders, multipliers) in high-performance microprocessors, though it remains susceptible to the charge-leakage and charge-sharing problems inherent to any dynamic logic family, requiring additional keeper-transistor or other charge-retention circuit techniques (examined in relation to another question in this examination) to maintain correct operation, particularly at the lower clock frequencies or larger fan-in gates where charge leakage has more time to corrupt the precharged dynamic node before evaluation completes."}]}},{"id":"vlsi-design-2021-7E1727-pC-q1","number":18,"marks":15,"tags":["Part C","Q.1"],"text":[{"type":"paragraph","content":"Q.1. Explain the dynamic behavior of MOSFET transistor with neat diagram. [15]"}],"answer":{"explanation":[{"type":"subheading","content":"Dynamic Behavior of MOSFET Transistor"},{"type":"svg","content":"","alt":"MOSFET cross section showing gate, source, drain regions and the parasitic capacitances Cgs, Cgd, Csb, Cdb that govern its dynamic switching behavior"},{"type":"paragraph","content":"The dynamic (switching) behavior of a MOSFET transistor, as distinct from its static (DC) current-voltage characteristics, is governed by several parasitic capacitances inherent to its physical structure, which must be charged or discharged whenever the transistor's terminal voltages change, and which therefore determine how quickly the device can actually switch states in a real circuit rather than switching instantaneously as an idealized model might suggest."},{"type":"paragraph","content":"The gate-to-source capacitance (Cgs) and gate-to-drain capacitance (Cgd) arise from the gate oxide's parallel-plate capacitance between the polysilicon gate electrode and the underlying channel/source/drain regions, and additionally include an overlap component where the gate physically overlaps the source and drain diffusion regions at the edges of the channel due to lateral diffusion during fabrication. The gate-to-drain overlap capacitance Cgd is of particular practical importance because of the Miller effect: in a common-source (inverting) amplifier or logic gate configuration, this capacitance appears between the input and output nodes, and because the output swings in the opposite direction to the input with some voltage gain, the effective input capacitance contributed by Cgd is multiplied by approximately (1+gain), making Cgd's effective loading impact on the driving stage considerably larger than its own nominal physical capacitance value would suggest."},{"type":"paragraph","content":"The source-to-body (Csb) and drain-to-body (Cdb) capacitances arise from the reverse-biased PN junctions formed between the n+ source/drain diffusion regions and the p-type substrate (for an NMOS device), behaving as voltage-dependent junction capacitances that decrease somewhat as the reverse bias across them increases (following the standard non-linear junction capacitance-versus-voltage relationship), and additionally including both a bottom-wall component (capacitance per unit area of the diffusion region's bottom surface facing the substrate) and a sidewall (perimeter) component (capacitance per unit length around the diffusion region's edge, often significant for the small diffusion areas typical of modern scaled transistors)."},{"type":"paragraph","content":"During a switching transition, these parasitic capacitances, together with any external load capacitance (wiring capacitance and the input capacitance of the following logic gate stage), must be charged or discharged through the transistor's own channel resistance (or, more precisely, through the transistor's actual nonlinear current-voltage characteristic in its triode and saturation regions, as examined in relation to the propagation delay derivation elsewhere in this examination) - the time required for this charging/discharging process, rather than any instantaneous switching, is what determines a real MOSFET circuit's actual achievable switching speed and propagation delay, and understanding and correctly modeling this complete set of parasitic capacitances (Cgs, Cgd with its Miller-multiplied effective value, Csb, Cdb, plus external wiring and fan-out load capacitance) is essential for accurate circuit-level timing simulation (SPICE-level modeling) and for informed transistor sizing decisions during VLSI circuit design, since simply assuming an idealized, capacitance-free switch (as might be done for purely logical/functional verification) would give no useful information about the actual achievable operating speed of a real fabricated circuit."},{"type":"paragraph","content":"Additionally, the channel charge itself (the mobile inversion-layer charge present when the transistor is ON) must be either supplied (when turning on) or removed (when turning off) through the source and drain terminals, contributing a further dynamic charging effect sometimes modeled as an additional channel charge capacitance partitioned between the source and drain terminals depending on the specific operating region (this channel-charge partitioning, and the associated charge-sharing/clock-feedthrough effects when a transistor switches off while charge is still present in its channel, is of particular practical importance in dynamic and switched-capacitor circuit design, including the domino logic and charge-sharing considerations examined in relation to other questions in this examination) - together, this complete picture of gate-oxide capacitance, junction capacitance, Miller-effect amplification, and channel-charge dynamics constitutes the full dynamic behavior model of a real MOSFET transistor as used in practical VLSI circuit design and simulation."},{"type":"paragraph","content":"It is also worth noting the practical circuit-design implications of the Miller-effect-amplified Cgd discussed above: because this effective input capacitance depends on the voltage gain of the stage being driven, a logic gate driving a following inverting stage sees a input capacitance that is not simply a fixed physical constant but depends on the specific gain of the load it drives, meaning accurate delay estimation for a chain of cascaded logic gates must account for this gain-dependent Miller multiplication at each stage rather than assuming a single fixed capacitance value for every gate, a subtlety that becomes especially important in analog and mixed-signal circuit design (where amplifier stages can have substantial voltage gain) though it is a comparatively smaller effect in typical digital logic gates operating with unity or near-unity voltage swing ratios."},{"type":"paragraph","content":"It is also worth noting that accurate SPICE-level circuit simulation models (such as the BSIM family of MOSFET compact models widely used in modern industrial VLSI design) represent all of these dynamic capacitance effects - gate-oxide capacitance including overlap terms, voltage-dependent junction capacitances with both bottom-wall and sidewall components, and channel-charge partitioning between source and drain - with considerably more mathematical sophistication and empirically-fitted parameters than the simplified textbook treatment given here, since accurately predicting circuit timing and power to within the tight margins required for successful first-pass silicon requires capturing second-order effects (velocity saturation, short-channel effects on capacitance, temperature dependence) well beyond the basic long-channel square-law capacitance model, though the fundamental physical origin of each capacitance component (gate-oxide, overlap, junction, channel-charge) remains exactly as described above regardless of the particular compact model's mathematical sophistication."},{"type":"paragraph","content":"In summary, correctly identifying and modeling each of these parasitic capacitance sources - gate-oxide, overlap-driven Miller-amplified Cgd, and voltage-dependent junction capacitances - together with the channel-charge dynamics during switching, provides the complete picture needed for accurate timing and power analysis of any real CMOS circuit built from these devices."},{"type":"paragraph","content":"This complete parasitic-capacitance and channel-charge picture is precisely what a circuit designer must understand and account for when performing transistor sizing trade-offs during physical design, since increasing a transistor's width to improve its drive strength and reduce delay simultaneously increases its own gate and junction capacitances, presenting a self-loading penalty that must be balanced against the drive-strength benefit for optimal circuit performance."},{"type":"paragraph","content":"This trade-off between drive strength and self-loading is a recurring theme across nearly every transistor-sizing decision made throughout VLSI physical design."}]}},{"id":"vlsi-design-2021-7E1727-pC-q2","number":19,"marks":15,"tags":["Part C","Q.2"],"text":[{"type":"paragraph","content":"Q.2. Write the layout design rules and draw diagram for four input NAND and NOR gate. [15]"}],"answer":{"explanation":[{"type":"subheading","content":"Layout Design Rules and Four-Input NAND/NOR Gate Layout"},{"type":"paragraph","content":"Layout design rules (commonly expressed as lambda-based rules, where lambda is a single process-dependent scaling parameter, allowing the same set of rules to be applied across different fabrication processes simply by changing the value of lambda) specify the minimum allowable dimensions and spacings for each mask layer used in a CMOS fabrication process, ensuring the resulting chip can be reliably manufactured without shorts, opens, or other defects caused by mask misalignment or process variation during fabrication."},{"type":"list","items":["Minimum width rules: specify the smallest allowable width for each layer (polysilicon gate width, typically 2*lambda; diffusion width, typically 3*lambda; metal width, typically 3*lambda), below which the manufacturing process cannot reliably produce a continuous, defect-free feature.","Minimum spacing rules: specify the smallest allowable separation between two features on the same layer (or between different layers that must not touch), such as minimum polysilicon-to-polysilicon spacing (2*lambda), minimum diffusion-to-diffusion spacing of the same type (3*lambda), and minimum spacing between n-diffusion and p-diffusion regions (typically larger, around 10*lambda, to accommodate the required well/tub boundary and prevent latch-up-related issues examined elsewhere in this examination).","Overlap and enclosure rules: specify the minimum extension of one layer beyond another at a contact or via (for example, metal must overlap a contact cut by at least 1*lambda on all sides, and diffusion or polysilicon must similarly overlap an underlying contact by a minimum amount) to guarantee reliable electrical contact despite mask alignment tolerances.","Extension rules: specify how far a gate polysilicon line must extend beyond the edge of the diffusion region it crosses (typically 2*lambda), ensuring the transistor's channel is fully defined even under worst-case mask misalignment, preventing an unintended direct short between source and drain diffusion."]},{"type":"svg","content":"","alt":"Four input NAND gate layout showing p-diffusion strip for four parallel PMOS transistors, n-diffusion strip for four series NMOS transistors, and four vertical polysilicon gate lines for inputs A B C D"},{"type":"paragraph","content":"A 4-input NAND gate requires 4 PMOS transistors connected in parallel (pull-up network, since the gate must pull the output high whenever ANY one of the four inputs is low) and 4 NMOS transistors connected in series (pull-down network, since the gate must pull the output low only when ALL four inputs are simultaneously high). In the layout, this is realized using two horizontal diffusion strips - a p-diffusion strip (within the n-well) accommodating the 4 parallel PMOS transistors, and an n-diffusion strip accommodating the 4 series NMOS transistors - with four vertical polysilicon gate lines crossing both diffusion strips, each polysilicon line corresponding to one input signal (A, B, C, D) and simultaneously forming the gate of both the corresponding PMOS transistor (in the upper strip) and NMOS transistor (in the lower strip)."},{"type":"paragraph","content":"For the series-connected NMOS pull-down network specifically, since all 4 NMOS transistors share the property that any two adjacent transistors in the series chain share a common diffusion node, the entire 4-transistor series chain can be laid out as a single continuous n-diffusion strip with the 4 polysilicon gates crossing it at 4 successive points, with metal contacts only needed at the two outer ends (one connecting to the output node, one connecting to ground) plus each internal series node remaining as bare diffusion without needing any contact at all - this Euler-path-style continuous diffusion layout (directly connecting to the Euler path concept examined in relation to another question in this examination) minimizes the diffusion area and eliminates unnecessary contacts compared to a naive layout that separately contacts and wires together four individually-placed transistors."},{"type":"svg","content":"","alt":"Four input NOR gate layout showing p-diffusion strip for four series PMOS transistors, n-diffusion strip for four parallel NMOS transistors, and four vertical polysilicon gate lines"},{"type":"paragraph","content":"A 4-input NOR gate has exactly the dual structure: 4 NMOS transistors in parallel (pull-down, output goes low whenever ANY input is high) and 4 PMOS transistors in series (pull-up, output goes high only when ALL inputs are simultaneously low) - the layout mirrors the NAND gate's structure with the series/parallel roles of the two diffusion strips exchanged, again exploiting the continuous-diffusion, minimum-contact layout technique for the series-connected (in this case, PMOS) transistor chain. In both the NAND and NOR layouts, all lambda-based design rules discussed above (minimum diffusion width, minimum polysilicon-to-polysilicon spacing between the four gate lines, minimum contact-to-diffusion-edge spacing at the output and supply/ground contacts, and adequate n-well-to-p-diffusion spacing at the boundary between the two diffusion strips) must be satisfied throughout the layout to ensure the gate can be reliably fabricated."},{"type":"paragraph","content":"It is also worth noting the practical trade-off inherent in choosing the value of lambda itself for a given fabrication process: a smaller lambda value allows more aggressive, denser layouts (smaller minimum feature sizes and spacings), directly reducing chip area and cost per die, but requires a correspondingly more advanced (and expensive) fabrication process capable of reliably manufacturing such small features with acceptable yield - this is precisely the parameter that scales down as semiconductor manufacturing technology advances from one process generation (technology node) to the next, and the lambda-based rule system's key practical advantage is that the same set of design rules (expressed purely as multiples of lambda) can be reused essentially unchanged across different process generations, simply substituting the new, smaller lambda value appropriate to the more advanced process, without needing to redesign the entire rule set from scratch for each new technology node."},{"type":"paragraph","content":"It is also worth explicitly noting why the n-diffusion-to-p-diffusion spacing rule is typically set considerably larger than same-type diffusion spacing rules: this larger spacing must accommodate the physical n-well (or p-well, depending on process type) boundary itself, which requires a certain minimum width to reliably contain the implanted/diffused well region and to maintain adequate spacing between the well edge and the adjacent diffusion regions of the opposite type, and this well-related spacing requirement is directly connected to preventing the parasitic latch-up phenomenon examined in detail elsewhere in this examination, since an inadequately-spaced n-diffusion-to-p-diffusion boundary increases the risk of triggering the parasitic bipolar PNPN thyristor structure inherent to any bulk CMOS process, making this particular spacing rule one of the most safety-critical design rules in the entire lambda-based rule set for reliable CMOS chip manufacturing."},{"type":"paragraph","content":"This complete treatment of lambda-based design rules, together with the specific layout structures for the four-input NAND and NOR gates, illustrates the essential bridge between a circuit's logical/schematic description and its final, physically manufacturable silicon implementation."},{"type":"paragraph","content":"This systematic, lambda-scalable design rule methodology, applied consistently across all mask layers in a given fabrication process, is precisely what allows large teams of VLSI designers to independently create different portions of a complex chip with confidence that their individually-designed blocks will integrate correctly and manufacture reliably once combined into the final full-chip layout."}]}},{"id":"vlsi-design-2021-7E1727-pC-q3","number":20,"marks":15,"tags":["Part C","Q.3"],"text":[{"type":"paragraph","content":"Q.3. Explain the static and dynamic power dissipation in CMOS circuits with necessary diagrams and expressions. [15]"}],"answer":{"explanation":[{"type":"subheading","content":"Static and Dynamic Power Dissipation in CMOS Circuits"},{"type":"paragraph","content":"Total power dissipation in a CMOS circuit is the sum of static power (dissipated continuously, regardless of switching activity) and dynamic power (dissipated only when the circuit actually switches states), and understanding and minimizing both components is a central concern of modern low-power VLSI design, particularly as CMOS technology has scaled to smaller feature sizes where static power has become an increasingly significant fraction of total power consumption."},{"type":"subheading","content":"Static Power Dissipation"},{"type":"paragraph","content":"Static power dissipation in an ideal CMOS gate would be exactly zero, since in any static logic state exactly one of the complementary pull-up/pull-down networks is fully OFF, blocking any DC current path from VDD to ground - however, real MOSFET transistors are never perfectly OFF, and several leakage mechanisms contribute non-zero static power even in a nominally quiescent (non-switching) CMOS circuit."},{"type":"math","expression":"P_{static} = I_{leakage} \\times V_{DD}","displayMode":true},{"type":"paragraph","content":"The dominant static leakage mechanisms are subthreshold conduction leakage (a transistor nominally 'off', with VGS below VT, still conducts a small but non-zero exponentially-decaying current, becoming increasingly significant as threshold voltages are scaled down in modern low-voltage processes to maintain adequate switching speed and drive current), reverse-biased junction leakage (the source/drain-to-substrate PN junctions, always reverse-biased in normal operation, still conduct a small reverse saturation current), and, in very deeply-scaled modern processes, gate oxide tunneling leakage (a small current tunneling directly through the increasingly thin gate oxide layer, becoming significant only in the most advanced nanometer-scale technology nodes)."},{"type":"subheading","content":"Dynamic Power Dissipation"},{"type":"paragraph","content":"Dynamic power dissipation, dominant in most conventional CMOS circuits operating at moderate-to-high switching activity, consists of two distinct components: switching (capacitive) power, dissipated whenever a load capacitance is charged from ground to VDD (drawing energy from the supply, half of which is stored on the capacitor and half dissipated as heat in the charging transistor's channel resistance) or discharged from VDD to ground (dissipating the previously-stored capacitor energy as heat in the discharging transistor), and short-circuit power, dissipated during the brief transition interval when both the PMOS and NMOS transistors of a CMOS gate are simultaneously partially ON (since a real, finite-slope input transition briefly puts both transistors into partial conduction as it crosses the switching threshold region), creating a brief direct current path from VDD to ground even though the gate itself is switching correctly."},{"type":"math","expression":"P_{switching} = \\alpha \\cdot C_L \\cdot V_{DD}^2 \\cdot f","displayMode":true},{"type":"paragraph","content":"The switching power expression above is the single most important and widely-used formula in CMOS power estimation: alpha is the switching activity factor (the average fraction of clock cycles during which a given node actually transitions, typically well below 1 for most real logic nodes, since not every gate switches on every single clock cycle), CL is the total load capacitance being charged/discharged at that node (including gate, junction, and wiring capacitance as examined in relation to the MOSFET dynamic behavior question elsewhere in this examination), VDD is the supply voltage, and f is the clock frequency - this expression's quadratic dependence on VDD is precisely why supply voltage scaling (reducing VDD) has historically been one of the single most effective techniques for reducing dynamic power consumption in successive CMOS technology generations, since halving VDD reduces switching power to one quarter, a far larger benefit than the corresponding linear reduction achievable by reducing capacitance or activity factor alone."},{"type":"math","expression":"P_{short-circuit} = I_{sc,avg} \\cdot V_{DD} \\propto t_{rise/fall} \\cdot V_{DD} \\cdot f","displayMode":true},{"type":"paragraph","content":"Short-circuit power depends on the input signal's rise/fall time (a slower, more gradual input transition keeps both transistors partially conducting for a longer overlap duration, increasing short-circuit power) and is generally kept to a modest fraction (typically 10-20%) of total dynamic power in a well-designed circuit with reasonably fast input transitions, but can become a much larger, problematic fraction of total power if a gate is driven by an excessively slow (poorly-buffered) input signal, making adequate buffer sizing and input slew-rate control an important practical CMOS design consideration for controlling this specific power component. The total power dissipation of a CMOS circuit is therefore the sum Ptotal = Pstatic + Pswitching + Pshort-circuit, and modern low-power VLSI design techniques specifically target each of these three components separately - multi-threshold and power-gating techniques to reduce static leakage, clock-gating and activity-factor reduction techniques to reduce switching power, and adequate buffer/driver sizing to control short-circuit power - reflecting the understanding that no single power-reduction technique alone can adequately address all three physically distinct power dissipation mechanisms present in real CMOS integrated circuits."},{"type":"paragraph","content":"It is also worth relating the switching-power formula's activity factor alpha to practical low-power design techniques used to reduce it directly: clock gating (disabling the clock input to a register or logic block during cycles when its output is not actually needed, preventing unnecessary switching activity in that block entirely) and operand isolation (freezing the inputs to an arithmetic unit such as a multiplier when its result is not needed in a given cycle, preventing wasted internal switching activity even though the unit's own clock continues toggling) are both widely used RTL and gate-level design techniques specifically targeting reduction of the effective activity factor alpha for portions of a chip that are not actively contributing useful computation in a given clock cycle, directly reducing switching power according to the formula derived above without requiring any change to supply voltage or clock frequency."},{"type":"paragraph","content":"It is also worth noting that the total chip-level power budget in a modern high-performance microprocessor or SoC is typically dominated by dynamic switching power at higher supply voltages and clock frequencies, but as supply voltage has been progressively scaled down across successive technology generations (following the quadratic dynamic-power-reduction incentive discussed above), static leakage power has grown to become a comparably significant, and in some low-power/mobile applications even dominant, fraction of total chip power, which is precisely why modern low-power VLSI design methodology treats static and dynamic power reduction as two equally important, complementary design objectives (multi-threshold cell libraries, power gating, and body-biasing techniques specifically targeting static leakage, alongside clock-gating, voltage-frequency scaling, and activity-factor-reduction techniques targeting dynamic power) rather than focusing on dynamic power alone as was more common in earlier, higher-supply-voltage CMOS technology generations."},{"type":"paragraph","content":"Altogether, this decomposition of total CMOS power dissipation into static, switching, and short-circuit components, together with the specific design techniques used to mitigate each, represents the standard analytical framework used throughout the modern low-power VLSI design industry."}]}},{"id":"vlsi-design-2021-7E1727-pC-q4","number":21,"marks":15,"tags":["Part C","Q.4"],"text":[{"type":"paragraph","content":"Q.4. Explain about building block architecture of FPGA. [15]"}],"answer":{"explanation":[{"type":"subheading","content":"FPGA Building Block Architecture"},{"type":"svg","content":"","alt":"FPGA building block architecture showing array of configurable logic blocks CLBs connected via programmable interconnect and surrounded by I/O blocks"},{"type":"paragraph","content":"The building block architecture of an FPGA (Field Programmable Gate Array) consists of three principal components: an array of Configurable Logic Blocks (CLBs, also called logic elements or logic cells depending on vendor terminology), a programmable interconnect (routing) fabric connecting these CLBs together and to the device's I/O pins, and Input/Output Blocks (IOBs) around the periphery of the device providing the programmable interface between the FPGA's internal logic and external circuit board signals."},{"type":"paragraph","content":"Each Configurable Logic Block is itself typically built from one or more Look-Up Tables (LUTs), small memory-based combinational logic elements that can be programmed to implement any Boolean function of their input variables (a k-input LUT, commonly 4-input or 6-input in modern FPGAs, can implement any of the 2^(2^k) possible Boolean functions of its k inputs, simply by loading the LUT's internal memory with the appropriate truth table), combined with a configurable flip-flop (allowing the LUT's combinational output to optionally be registered, enabling sequential logic implementation), and additional configurable multiplexers and carry-chain logic (dedicated fast-carry circuitry specifically optimized for efficient implementation of adders and other arithmetic functions spanning multiple CLBs)."},{"type":"paragraph","content":"The programmable interconnect fabric consists of a network of wire segments of various lengths (short segments connecting adjacent CLBs, longer segments spanning greater distances across the chip) and programmable switch/routing matrices at the intersections of these wire segments, allowing the physical design/place-and-route software to establish the specific signal connections required by a given user design by programming the appropriate switches to connect the correct combination of wire segments together - this segmented, distributed interconnect structure (as opposed to a single centralized interconnect matrix, characteristic instead of the simpler CPLD architecture examined in relation to another question in this examination) is what allows FPGAs to scale to very large logic capacities while still achieving reasonably efficient, low-congestion routing for typical real-world designs."},{"type":"paragraph","content":"Modern FPGAs additionally incorporate dedicated hard-macro blocks embedded within the CLB array to improve efficiency for common, resource-intensive functions that would otherwise consume disproportionate LUT-based logic resources if implemented purely from generic CLBs: block RAM (BRAM) modules providing dedicated, efficient on-chip memory storage; dedicated DSP (Digital Signal Processing) blocks providing hardware multiply-accumulate units optimized for signal-processing and arithmetic-intensive applications; and, in the largest and most advanced modern FPGAs, embedded hard processor cores (such as an ARM Cortex processor) and high-speed serial transceivers for gigabit-per-second communication interfaces, together transforming the modern FPGA from a purely programmable-logic device into what is often now termed a 'System-on-Chip' (SoC) FPGA, combining reconfigurable logic fabric with substantial dedicated, hard-wired functional blocks on a single device."},{"type":"paragraph","content":"The Input/Output Blocks at the periphery of the FPGA provide programmable buffering, voltage-level translation, and I/O standard selection (supporting a range of different signaling voltage standards and protocols such as LVCMOS, LVDS, and others) for each physical device pin, allowing the same FPGA device to be configured for compatibility with a wide range of different external interface voltage standards and signaling protocols depending on the specific target application's board-level interface requirements, without requiring a different physical device variant for each possible I/O standard combination."},{"type":"paragraph","content":"It is also worth comparing this FPGA building-block architecture explicitly against the simpler CPLD architecture discussed elsewhere in this examination: whereas an FPGA's fine-grained LUT-based CLBs and distributed, segmented interconnect fabric together allow it to scale efficiently to very large logic capacities (millions of equivalent logic gates in the largest modern devices), a CPLD's coarser-grained, macrocell-based architecture with a centralized, near-fully-connected interconnect matrix gives it more predictable, fixed timing and non-volatile instant-on configuration, but at the cost of much more limited achievable logic capacity, since a fully-connected centralized interconnect matrix becomes prohibitively large and slow to implement as the number of logic blocks grows much beyond a few hundred - this fundamental architectural trade-off between fine-grained scalability (FPGA) and coarse-grained predictability (CPLD) is precisely why the two device families continue to coexist for different application niches rather than one architecture having entirely displaced the other."},{"type":"paragraph","content":"It is also worth noting the specific role of the carry-chain logic mentioned within each CLB: because implementing wide arithmetic operations (such as a 32-bit or 64-bit adder) purely from generic LUT-based combinational logic would require an impractically large ripple-carry propagation delay through many cascaded LUT stages, modern FPGA CLB architectures include a dedicated, hard-wired fast-carry interconnect path specifically optimized (using specialized, minimal-delay carry-propagate circuitry bypassing the general-purpose programmable interconnect fabric entirely) to allow a carry signal to ripple efficiently from one CLB to the next along an arithmetic chain, dramatically improving the achievable clock frequency of FPGA-implemented arithmetic circuits compared to what would be achievable using only the general-purpose LUT and interconnect resources for carry propagation."},{"type":"paragraph","content":"This complete picture of CLBs, programmable interconnect, I/O blocks, and embedded hard macros together explains why FPGAs have become the platform of choice for an enormously broad range of applications, from rapid prototyping through to high-volume production of moderate-complexity digital systems."},{"type":"paragraph","content":"It is also worth noting the software toolchain that accompanies this hardware architecture: FPGA vendors provide dedicated place-and-route and bitstream-generation software specifically tailored to their own device's CLB and interconnect architecture, meaning a synthesized netlist for one vendor's FPGA family generally cannot be directly ported to a different vendor's device without re-running the full synthesis, placement, and routing flow using that vendor's own toolchain, in contrast to ASIC design where a synthesized netlist is comparatively more portable across different standard-cell libraries and foundries provided the target technology characteristics are reasonably similar."},{"type":"paragraph","content":"This device-specific toolchain dependency, together with the architectural differences from CPLDs discussed above, together explain why selecting the right programmable logic family and vendor for a given project requires careful upfront consideration of logic capacity, required hard-IP blocks, toolchain maturity, and long-term product availability, rather than treating FPGA selection as a purely interchangeable commodity decision."},{"type":"paragraph","content":"Such long-term availability and toolchain-continuity considerations are just as important to a successful FPGA-based product as the underlying logic capacity and architecture itself."},{"type":"paragraph","content":"A thoughtfully chosen FPGA platform, matched to both present logic requirements and anticipated future design revisions, avoids costly redesign efforts later in a product's lifecycle."}]}},{"id":"vlsi-design-2021-7E1727-pC-q5","number":22,"marks":15,"tags":["Part C","Q.5"],"text":[{"type":"paragraph","content":"Q.5. What do you mean by VHDL? Write a VHDL code for - (a) Full Adder (b) D Flip-flop. [15]"}],"answer":{"explanation":[{"type":"subheading","content":"VHDL - Definition, Full Adder, and D Flip-flop"},{"type":"paragraph","content":"VHDL (VHSIC Hardware Description Language, where VHSIC stands for Very High Speed Integrated Circuit) is a standardized (IEEE 1076) hardware description language used to describe, simulate, and synthesize digital electronic circuits and systems at multiple levels of abstraction, from high-level behavioral algorithmic descriptions down to detailed gate-level structural descriptions, originally developed in the early 1980s under a US Department of Defense program and subsequently becoming one of the two dominant hardware description languages (alongside Verilog) used throughout the digital IC and FPGA design industry, allowing a design to be captured in text form, verified through simulation against a testbench, and automatically synthesized into an actual gate-level netlist implementation for a target FPGA or ASIC technology."},{"type":"subheading","content":"(a) VHDL Code for Full Adder"},{"type":"code-block","language":"vhdl","content":"library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nentity full_adder is\n port (\n A, B, Cin : in STD_LOGIC;\n Sum, Cout : out STD_LOGIC\n );\nend full_adder;\n\narchitecture dataflow of full_adder is\nbegin\n Sum <= A xor B xor Cin;\n Cout <= (A and B) or (B and Cin) or (A and Cin);\nend dataflow;"},{"type":"paragraph","content":"This full adder takes three single-bit inputs (A, B, and carry-in Cin) and produces a Sum output (the three-input XOR of the inputs, giving 1 whenever an odd number of the inputs are 1) and a Cout carry-out output (1 whenever at least two of the three inputs are 1, expressed as the OR of the three pairwise AND terms), implemented as a purely combinational circuit using concurrent dataflow-style signal assignments that directly express the standard full-adder Boolean equations."},{"type":"subheading","content":"(b) VHDL Code for D Flip-flop"},{"type":"code-block","language":"vhdl","content":"library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nentity d_ff is\n port (\n clk, reset, D : in STD_LOGIC;\n Q : out STD_LOGIC\n );\nend d_ff;\n\narchitecture behavioral of d_ff is\n signal Q_int : STD_LOGIC := '0';\nbegin\n process(clk, reset)\n begin\n if reset = '1' then\n Q_int <= '0';\n elsif rising_edge(clk) then\n Q_int <= D;\n end if;\n end process;\n Q <= Q_int;\nend behavioral;"},{"type":"paragraph","content":"This D flip-flop is written using a behavioral, process-based VHDL description, the standard technique for describing edge-triggered sequential logic: the process is sensitive to both clk and reset, giving the flip-flop an asynchronous reset (immediately forcing Q to 0 whenever reset is asserted, regardless of the clock), and on every rising edge of the clock (detected using the standard, synthesizable 'rising_edge' function), the flip-flop's stored value Q_int is updated to simply equal the current value of the data input D, exactly implementing the D flip-flop's defining behavior of sampling and holding its input value once per clock cycle. An internal signal Q_int is used within the process (rather than directly assigning to the output port Q) and then continuously assigned to the actual output port outside the process, a standard VHDL coding idiom needed because reading back the value of an 'out' mode port signal directly is not permitted in some VHDL versions/tool configurations."},{"type":"paragraph","content":"It is also worth noting VHDL's broader position within the overall VLSI design flow discussed elsewhere in this examination: the VHDL source code written for the full adder and D flip-flop above represents the RTL (Register Transfer Level) description stage of the design flow, which is subsequently verified through functional simulation against a testbench (applying test input stimuli and checking the resulting outputs match expected values), then synthesized into a gate-level netlist targeting a specific FPGA or ASIC technology library, and finally placed, routed, and (for an ASIC) fabricated, or (for an FPGA) configured onto the target programmable device - VHDL therefore serves as the foundational entry point for essentially the entire modern digital VLSI design process, from initial design capture through to final silicon or FPGA bitstream implementation."},{"type":"paragraph","content":"VHDL's advantages, beyond its role in this design flow, include its strong, standardized (IEEE 1076) type system (catching many design errors at compile time before simulation even begins, such as connecting ports of mismatched width or type), its support for multiple levels of design abstraction within a single language (behavioral, dataflow, and structural styles, as illustrated by the two different but complementary coding styles used for the full adder - a purely dataflow/Boolean-equation style - and the D flip-flop - a behavioral, process-based style - in this answer), and its strong support for design reuse through packages, generics, and hierarchical component instantiation, making VHDL well suited to managing the complexity of large, multi-million-gate modern digital designs built up from many reusable sub-modules."},{"type":"paragraph","content":"VHDL's limitations include its comparatively verbose syntax (requiring more boilerplate declaration code than some alternative hardware description languages for equivalent designs) and the important practical distinction that only a subset of the full VHDL language is actually synthesizable into real hardware, meaning designers must learn and consistently apply synthesizable coding-style guidelines (avoiding simulation-only constructs such as arbitrary delay values, file I/O, or certain loop constructs that have no direct physical hardware equivalent) to ensure their VHDL code can actually be converted into working silicon or FPGA logic by a synthesis tool, rather than remaining only a functionally-correct simulation model with no direct hardware-implementation pathway."},{"type":"paragraph","content":"Both example circuits given above - the full adder and the D flip-flop - are foundational building blocks used extensively throughout digital VLSI design: full adders are cascaded to build multi-bit ripple-carry or more advanced carry-lookahead adders (the basic arithmetic building block of essentially every digital processor's arithmetic logic unit), while D flip-flops are the fundamental storage element used to build registers, counters, shift registers, and the state-holding elements of finite state machines throughout sequential digital circuit design - together, these two examples illustrate both the purely combinational (dataflow-style) and purely sequential (clocked, behavioral-style) VHDL coding paradigms that, in combination, are sufficient to describe essentially any digital circuit of arbitrary complexity, from these simple building blocks up to complete modern microprocessors and system-on-chip designs."},{"type":"paragraph","content":"In summary, defining VHDL's role and scope, then demonstrating both its dataflow and behavioral coding styles through the full adder and D flip-flop examples respectively, provides a complete, self-contained introduction to how digital circuits are captured, verified, and ultimately implemented using this foundational hardware description language."},{"type":"paragraph","content":"Finally, it is worth noting that both example designs given here were deliberately kept simple to clearly illustrate the underlying coding style distinction, but the exact same dataflow-versus-behavioral technique scales directly to arbitrarily complex real-world designs, meaning a student who understands these two small examples has grasped the fundamental coding pattern used throughout virtually every larger VHDL design, from simple combinational adders and flip-flops up through complete processor datapaths and control units."},{"type":"paragraph","content":"This transferability of the underlying coding technique is exactly why these two small building blocks are such standard, widely-used introductory VHDL teaching examples."},{"type":"paragraph","content":"Their simplicity is exactly what makes them effective teaching tools for the underlying VHDL concepts they demonstrate."},{"type":"paragraph","content":"A student who has fully internalized these two worked examples is well prepared to tackle considerably more elaborate VHDL design exercises with confidence."}]}}],"examYear":2021},{"id":"vlsi-design-2021-7E7084","title":"VLSI Design (Feb-March 2021, Back)","subjectSlug":"vlsi-design","subjectName":"VLSI Design","universitySlug":"rtu","branchSlug":"ee-ec-eee","year":4,"semester":7,"paperCode":"7E7084","questions":[{"id":"vlsi-design-2021-7E7084-u1-q1","number":1,"marks":16,"tags":["Unit I","Q.1"],"text":[{"type":"paragraph","content":"Q.1. (a) Draw and write the working of enhancement mode PMOS with the help of input-output and transfer characteristics. [8]"},{"type":"paragraph","content":"(b) Write the names and compare the three technologies used for the fabrication of CMOS transistor. [8]"}],"answer":{"summary":"","explanation":[]}},{"id":"vlsi-design-2021-7E7084-u1-q1or","number":2,"marks":16,"tags":["Unit I","Q.1 OR"],"text":[{"type":"paragraph","content":"Q.1. (a) What are the different factors affecting the threshold voltage of MOSFET? Derive the formula used. Also, derive the body effect coefficient. [8]"},{"type":"paragraph","content":"(b) Draw MOS transistor circuit model and explain the origination of each parameter. [8]"}],"answer":{"summary":"","explanation":[]}},{"id":"vlsi-design-2021-7E7084-u2-q2","number":3,"marks":16,"tags":["Unit II","Q.2"],"text":[{"type":"paragraph","content":"Q.2. (a) Draw voltage transfer characteristics (VTC) of CMOS inverter and derive the expression for Bn/Bp ratio. [8]"},{"type":"paragraph","content":"(b) Write the names of three types of power dissipation in CMOS logic circuits and derive the expression for total power dissipation. [8]"}],"answer":{"summary":"","explanation":[]}},{"id":"vlsi-design-2021-7E7084-u2-q2or","number":4,"marks":16,"tags":["Unit II","Q.2 OR"],"text":[{"type":"paragraph","content":"Q.2. (a) Design the following logic circuits using CMOS logic gate - (i) 3-input NAND gate (ii) S-R Flip-flop [8]"},{"type":"paragraph","content":"(b) Implement the Boolean expression F=a.(b+b'c') using CMOS logic and also determine the size of each transistor using equivalent inverter transistor sizes. [8]"}],"answer":{"summary":"","explanation":[]}},{"id":"vlsi-design-2021-7E7084-u3-q3","number":5,"marks":16,"tags":["Unit III","Q.3"],"text":[{"type":"paragraph","content":"Q.3. (a) Implement 2x1 multiplexer using transmission gate and draw its layout. [8]"},{"type":"paragraph","content":"(b) Draw Euler path and layout diagram for 3-input NOR gate and mark all the size/spacing using lambda-rules. [8]"}],"answer":{"summary":"","explanation":[]}},{"id":"vlsi-design-2021-7E7084-u3-q3or","number":6,"marks":16,"tags":["Unit III","Q.3 OR"],"text":[{"type":"paragraph","content":"Q.3. (a) What is latch-up problem in CMOS? Draw and explain its physical origin, model and V-I characteristics. [8]"},{"type":"paragraph","content":"(b) Write the names and explain the techniques used to prevent latch-up problem. [8]"}],"answer":{"summary":"","explanation":[]}},{"id":"vlsi-design-2021-7E7084-u4-q4","number":7,"marks":16,"tags":["Unit IV","Q.4"],"text":[{"type":"paragraph","content":"Q.4. (a) Compare NORA and NP (ZIPPER) CMOS logic structures. [8]"},{"type":"paragraph","content":"(b) Explain various circuit techniques used in domino CMOS circuits for solving charge sharing problem. [8]"}],"answer":{"summary":"","explanation":[]}},{"id":"vlsi-design-2021-7E7084-u4-q4or","number":8,"marks":16,"tags":["Unit IV","Q.4 OR"],"text":[{"type":"paragraph","content":"Q.4. Draw a circuit diagram of a DRAM cell and explain the following operations - (i) Synchronous read mode (ii) Asynchronous read mode (iii) Leakage currents and refresh operation. [8]"},{"type":"paragraph","content":"(b) Draw SRAM cell and explain its write and read operation with appropriate timing diagram. [8]"}],"answer":{"summary":"","explanation":[]}},{"id":"vlsi-design-2021-7E7084-u5-q5","number":9,"marks":16,"tags":["Unit V","Q.5"],"text":[{"type":"paragraph","content":"Q.5. (a) Draw VHDL/PLD based ASIC design flow block diagram. Explain each step involved. [8]"},{"type":"paragraph","content":"(b) Write VHDL code for positive edge triggered S-R flip-flop. [8]"}],"answer":{"summary":"","explanation":[]}},{"id":"vlsi-design-2021-7E7084-u5-q5or","number":10,"marks":16,"tags":["Unit V","Q.5 OR"],"text":[{"type":"paragraph","content":"Q.5. (a) Write VHDL code for half adder in structural style. [8]"},{"type":"paragraph","content":"(b) Write VHDL model for left to right shift register using enable input. [8]"}],"answer":{"summary":"","explanation":[]}}],"examYear":2021},{"id":"vlsi-design-2019-7E7084","title":"VLSI Design (Nov 2019)","subjectSlug":"vlsi-design","subjectName":"VLSI Design","universitySlug":"rtu","branchSlug":"ee-ec-eee","year":4,"semester":7,"paperCode":"7E7084","questions":[{"id":"vlsi-design-2019-7E7084-u1-q1","number":1,"marks":16,"tags":["Unit I","Q.1"],"text":[{"type":"paragraph","content":"1. (a) Develop the relation between Ids and Vds for MOSFET and modify it under channel length modulation. [8]"},{"type":"paragraph","content":"(b) Draw variation of gate oxide capacitance with Vds. Assume the gate voltage Vgs > Vth. [6]"},{"type":"paragraph","content":"(c) State the condition of ohmic operation. [2]"}],"answer":{"explanation":[{"type":"subheading","content":"Ids-Vds Relation for MOSFET, Channel Length Modulation, Gate Oxide Capacitance, and Ohmic Condition"},{"type":"math","content":"I_{DS} = \\mu_n C_{ox} \\frac{W}{L}\\left[(V_{GS}-V_{TH})V_{DS} - \\frac{V_{DS}^2}{2}\\right] \\quad (\\text{triode/linear region, } V_{DS} < V_{GS}-V_{TH})"},{"type":"paragraph","content":"The basic MOSFET drain current equation is derived from the charge-sheet model, where the mobile inversion-layer charge per unit area at a point y along the channel is Qi(y) = Cox[VGS - V(y) - VTH], V(y) being the channel potential at that point relative to the source. The drain current, being the same at every point along the channel by current continuity, is IDS = W*mu_n*Qi(y)*dV/dy. Integrating this expression along the channel length from y=0 (V=0) to y=L (V=VDS) yields the triode-region equation IDS = mu_n*Cox*(W/L)*[(VGS-VTH)*VDS - VDS^2/2], valid as long as the transistor remains in the triode (ohmic/linear) region."},{"type":"math","content":"I_{DS} = \\frac{\\mu_n C_{ox}}{2}\\frac{W}{L}(V_{GS}-V_{TH})^2 \\quad (\\text{saturation region, } V_{DS} \\geq V_{GS}-V_{TH})"},{"type":"paragraph","content":"As VDS is increased, the inversion charge density at the drain end of the channel, Qi(L) = Cox[VGS - VDS - VTH], progressively decreases, reaching exactly zero when VDS = VGS - VTH = VDSAT, a condition called pinch-off. Beyond this point (VDS > VDSAT), substituting VDS = VDSAT into the triode equation and simplifying gives the saturation-region drain current IDS = (mu_n*Cox/2)*(W/L)*(VGS-VTH)^2, which in the ideal long-channel model is independent of VDS beyond pinch-off, producing a flat IDS-VDS characteristic in saturation."},{"type":"paragraph","content":"In a real, finite-length MOSFET, however, the pinch-off point does not remain fixed at y=L as VDS increases beyond VDSAT; instead, the channel physically shortens as the pinch-off point moves toward the source, with the effective channel length reducing from L to L' = L - deltaL, where deltaL grows with (VDS - VDSAT). This phenomenon, called channel length modulation (CLM), causes the saturation current to keep rising slightly with VDS rather than remaining perfectly flat, since IDS is inversely proportional to the effective channel length."},{"type":"math","content":"I_{DS} = \\frac{\\mu_n C_{ox}}{2}\\frac{W}{L}(V_{GS}-V_{TH})^2 (1 + \\lambda V_{DS})"},{"type":"paragraph","content":"This modified saturation-current equation introduces the channel length modulation parameter lambda (units of 1/V), an empirically extracted parameter inversely related to the channel length L (longer-channel devices show smaller lambda and hence flatter output characteristics, while short-channel devices show pronounced current increase with VDS). Physically, lambda models the finite output resistance ro = 1/(lambda*IDS) of the MOSFET in saturation, a parameter of central importance in analog amplifier design since it directly sets the maximum achievable intrinsic voltage gain (gm*ro) of a single transistor."},{"type":"subheading","content":"Gate Oxide Capacitance Variation with VDS"},{"type":"paragraph","content":"The gate-to-channel (oxide) capacitance Cgc is not constant across all operating regions but varies with the terminal voltages because the underlying MOS structure's capacitance depends on which of accumulation, depletion, or inversion condition exists beneath the gate. With VGS > VTH so the channel is in strong inversion (as stated in the question), the relevant variation is with VDS at fixed VGS > VTH: in the cutoff/subthreshold region the capacitance would be dominated by the depletion capacitance, but since the device is biased in strong inversion here, in the triode region (small VDS) the full gate oxide capacitance Cox*W*L is essentially shared equally between the gate-to-source and gate-to-drain overlap-plus-channel capacitances (Cgs ≈ Cgd ≈ Cox*W*L/2), giving a large total gate capacitance."},{"type":"paragraph","content":"As VDS increases toward and beyond VDSAT into the saturation region, the channel pinches off near the drain, electrically disconnecting the drain end of the channel from the gate capacitively; the charge-partitioning models (commonly the 40/60 or similar partition used in SPICE-level MOSFET models) then assign roughly 0% of the channel charge to Cgd (only the small overlap capacitance remains) and about 2/3 (or a similarly weighted majority) of the total channel charge to Cgs. Consequently, as VDS is swept from zero (triode) into saturation, Cgd falls sharply from about Cox*W*L/2 down to just the gate-drain overlap capacitance, while Cgs approaches a value close to (2/3)*Cox*W*L, so a plot of gate capacitance versus VDS shows Cgs rising and Cgd falling as VDS crosses VDSAT, with the total gate capacitance Cgc = Cgs + Cgd settling to a lower combined value in deep saturation than in the triode region."},{"type":"subheading","content":"Condition for Ohmic (Triode) Operation"},{"type":"paragraph","content":"A MOSFET operates in the ohmic (also called triode or linear) region whenever the gate-to-source voltage exceeds threshold (VGS > VTH, so a conducting channel exists) AND the drain-to-source voltage remains below the overdrive voltage, i.e., VDS < (VGS - VTH) = VDSAT. Under this condition, the channel exists continuously from source to drain without pinch-off, and the device behaves approximately as a voltage-controlled resistor for small VDS, which is why this region is also called the resistive or linear region - this is the operating condition explicitly assumed for the small-VDS gate-capacitance discussion above."},{"type":"paragraph","content":"It is instructive to note the practical significance of channel length modulation in circuit design: while the ideal square-law model predicts a MOSFET behaves as a perfect current source in saturation (infinite output resistance), the lambda term means every real transistor has finite output resistance ro, which directly limits the maximum voltage gain obtainable from a single common-source amplifier stage to roughly gm*ro. As technology scales to shorter channel lengths, lambda increases (since deltaL becomes a proportionally larger fraction of the now-smaller L), causing ro to shrink and intrinsic gain per stage to degrade, which is one of the central reasons modern analog circuit design in deep-submicron CMOS increasingly relies on cascode structures and multi-stage gain-boosting techniques rather than simple single-transistor amplifier stages."},{"type":"paragraph","content":"Regarding gate oxide capacitance behavior, it is also worth emphasizing that this VDS-dependent partitioning of the total gate capacitance between Cgs and Cgd (via the charge-sharing models used in circuit simulators such as SPICE) has direct consequences for high-frequency and transient circuit analysis: because Cgd shrinks substantially once the device enters saturation, the Miller-multiplied effect of Cgd on the effective input capacitance of an inverting amplifier stage is much smaller in saturation than it would be if the device were biased in the triode region, an important consideration when estimating propagation delay and bandwidth in cascaded digital or analog CMOS stages."},{"type":"paragraph","content":"Finally, the ohmic (triode) operating condition VDS < VGS - VTH is the regime in which a MOSFET is most commonly used as a pass transistor or as the pull-down/pull-up device of a digital logic gate driving a small output voltage swing, since in this region the device presents a well-defined, gate-voltage-controllable channel resistance rather than acting as a current source - this resistive behavior is precisely what is exploited in ratioed logic families (such as the NMOS active-load inverter discussed elsewhere in this examination) where the driver transistor is deliberately operated deep into the triode region to pull the output down to a well-defined low logic level."}]}},{"id":"vlsi-design-2019-7E7084-u1-q1or","number":2,"marks":16,"tags":["Unit I","Q.1 OR"],"text":[{"type":"paragraph","content":"1. (a) Find the expression of threshold voltage Vtho and discuss how it modified under body bias. [8]"},{"type":"paragraph","content":"(b) Discuss any two phenomena in MOSFET from - (i) Hot electron effect (ii) Subthreshold conduction (iii) Narrow channel effect. [4+4=8]"}],"answer":{"explanation":[{"type":"subheading","content":"Threshold Voltage Expression, Body Bias Effect, and MOSFET Non-Ideal Phenomena"},{"type":"math","content":"V_{THO} = V_{FB} + 2\\phi_F + \\frac{\\sqrt{2 q \\varepsilon_{si} N_A (2\\phi_F)}}{C_{ox}}"},{"type":"paragraph","content":"The zero-body-bias threshold voltage VTHO of an NMOS transistor is derived by requiring the surface potential to reach strong inversion (surface potential = 2*phi_F, where phi_F = (kT/q)*ln(NA/ni) is the Fermi potential of the p-type substrate). VTHO comprises three physically distinct terms: VFB, the flat-band voltage (accounting for the work-function difference between gate and substrate materials plus any fixed oxide charge); 2*phi_F, the band-bending required at the surface to achieve strong inversion; and the depletion-charge term sqrt(2*q*epsilon_si*NA*2*phi_F)/Cox, which represents the additional gate voltage needed to support the depletion-region charge QB0 = sqrt(2*q*epsilon_si*NA*2*phi_F) that forms beneath the gate before inversion charge can accumulate, divided by the oxide capacitance per unit area Cox = epsilon_ox/tox to convert this charge into an equivalent voltage."},{"type":"math","content":"V_{TH} = V_{THO} + \\gamma\\left(\\sqrt{2\\phi_F + V_{SB}} - \\sqrt{2\\phi_F}\\right), \\quad \\gamma = \\frac{\\sqrt{2 q \\varepsilon_{si} N_A}}{C_{ox}}"},{"type":"paragraph","content":"When a reverse body-to-source bias VSB is applied (source held at higher potential than the body/substrate for an NMOS device, as is standard practice to keep the source-body junction reverse-biased), the depletion region beneath the channel widens further, requiring additional depletion charge to be supported, which in turn requires additional gate voltage to reach inversion. This is captured by the body-effect equation above, where gamma is the body-effect coefficient. Since VTH increases with increasing VSB, stacked NMOS transistors in a logic gate (where upper transistors see a nonzero source-to-body voltage due to the voltage drop across lower transistors) exhibit a higher effective threshold voltage than the bottom transistor, an effect that must be accounted for in accurate delay and noise-margin analysis of series-connected MOS logic structures."},{"type":"subheading","content":"Hot Electron Effect"},{"type":"paragraph","content":"The hot-electron effect occurs in short-channel MOSFETs where the lateral electric field near the drain end of the channel becomes very large (due to the short channel length concentrating the full VDS drop over a very small distance). Channel electrons accelerated by this intense field can gain kinetic energy far exceeding the thermal equilibrium value, becoming 'hot' carriers. Some of these hot electrons possess enough energy to surmount the Si-SiO2 interface energy barrier and become injected into the gate oxide, where they can become trapped as fixed oxide charge or interface-state charge near the drain. This trapped charge causes a long-term, cumulative shift in threshold voltage and transconductance (a reliability degradation mechanism), and can also generate substrate current via impact ionization, both effects that worsen as channel lengths are scaled down and lateral fields increase, making hot-carrier degradation one of the primary long-term reliability concerns in deep-submicron CMOS technology."},{"type":"subheading","content":"Subthreshold Conduction"},{"type":"paragraph","content":"Subthreshold conduction refers to the small but nonzero drain current that flows even when VGS is below VTH, in the regime where the surface is in weak inversion rather than fully off. Rather than the square-law behavior of strong inversion, subthreshold current follows an exponential dependence on VGS, IDS,sub proportional to exp(VGS/(n*VT)), where VT = kT/q is the thermal voltage and n is the subthreshold slope (ideality) factor, typically between 1 and 2 depending on the depletion capacitance to oxide capacitance ratio. This exponential 'subthreshold leakage' current is not merely a curiosity - it is the dominant source of static (off-state) power dissipation in modern low-VTH, low-supply-voltage digital ICs, since a 'logically off' transistor never truly shuts off completely, and this leakage scales the total standby power of very-large-scale, densely-integrated chips containing billions of transistors, making subthreshold leakage control (via multiple-VTH design, power gating, and body biasing) a central concern of modern low-power VLSI design."},{"type":"paragraph","content":"The body effect has significant practical implications in digital circuit design beyond the simple stacked-transistor threshold-shift observation made above. In particular, in dynamic and pass-transistor logic circuits where a MOSFET's source terminal is not held at a fixed reference potential (unlike in standard static CMOS gates where NMOS sources are always tied to ground and PMOS sources to VDD), the body effect can cause substantial, signal-dependent threshold-voltage variation that must be accounted for when sizing transistors and estimating worst-case propagation delay, since the effective drive strength of the transistor changes as VSB varies with the signal being processed."},{"type":"paragraph","content":"Narrow-channel effect, the third listed phenomenon, arises when the transistor's channel width W becomes comparable to or smaller than the width of the depletion region extending laterally from the channel edges (beneath the field-oxide isolation bounding the active area). In wide-channel devices, this lateral depletion region is a negligible fraction of the total channel width and can be ignored, but as W is scaled down in modern narrow-channel devices, the additional depletion charge contributed by these lateral edge regions becomes a significant fraction of the total depletion charge under the gate, causing the effective threshold voltage to increase above the value predicted by the simple one-dimensional threshold voltage model - this narrow-channel threshold increase is the width-scaling counterpart to the short-channel effect (where threshold voltage decreases as channel length is scaled down due to charge-sharing from the source/drain depletion regions), and both effects must be characterized and compensated for via process-level threshold-adjustment implants in modern scaled CMOS technology to maintain predictable, uniform threshold voltages across transistors of different sizes on the same chip."},{"type":"paragraph","content":"Taken together, these non-ideal short-channel and narrow-channel phenomena (hot-electron degradation, subthreshold leakage, and narrow-channel threshold shift) represent the central physical limitations that circuit and process designers must manage as CMOS technology continues to scale to smaller geometries, and understanding their combined effect on threshold voltage, leakage current, and long-term reliability is essential for accurate SPICE-level device modeling (via BSIM and similar industry-standard compact models) used throughout modern digital and analog IC design flows."},{"type":"paragraph","content":"These considerations collectively explain why accurate SPICE-level compact models (BSIM3, BSIM4, and their successors) devote enormous mathematical complexity specifically to capturing body-effect, hot-carrier, subthreshold, and narrow-channel behavior with high fidelity, since even small modeling inaccuracies in these effects can translate into large timing and power-estimation errors when applied across a modern chip containing many millions or billions of transistors operating under widely varying local bias conditions."},{"type":"paragraph","content":"Foundries therefore characterize and specify separate hot-carrier lifetime, subthreshold slope, and width-dependent threshold parameters for every transistor flavor offered in a given process node, and circuit designers must consult these characterization curves whenever pushing a design toward its absolute performance or reliability limits."}]}},{"id":"vlsi-design-2019-7E7084-u2-q2","number":3,"marks":16,"tags":["Unit II","Q.2"],"text":[{"type":"paragraph","content":"2. (a) Draw NMOS inverter with active load and draw its Transfer characteristic. Also find the expression VIL, VIH, VOL and VOH for it. [10]"},{"type":"paragraph","content":"(b) Draw y = A + B'C using CMOS. [6]"}],"answer":{"explanation":[{"type":"subheading","content":"NMOS Inverter with Active Load: Transfer Characteristic and VIL, VIH, VOL, VOH"},{"type":"svg","content":"","alt":"NMOS inverter circuit with an enhancement-mode active load transistor stacked above the driver transistor"},{"type":"paragraph","content":"In an NMOS inverter with an active (enhancement or depletion) load, the load transistor's gate is tied either to VDD (enhancement load, saturated-load configuration) or to its own source (depletion load), while the driver transistor's gate receives the input Vin and its drain is the output node Vout. Unlike a resistive load, the active load is itself a nonlinear MOSFET, so the transfer characteristic (VTC) must be derived by equating the driver and load currents (KCL: current through load = current through driver, since they are in series) across each combination of operating regions."},{"type":"paragraph","content":"For an enhancement-load NMOS inverter, the load transistor's gate-source voltage is fixed at VGS,load = VDD - Vout, so the load remains in saturation for essentially the entire useful output range (since VDD - Vout typically exceeds the load's VDSAT). The load current is therefore ID,load = (k_load/2)*(VDD - Vout - VTH)^2, a constant-ish 'current source' characteristic modulated slightly by Vout. The driver, with VGS,driver = Vin, transitions between cutoff, triode, and saturation as Vin sweeps from 0 to VDD, producing the characteristic VTC breakpoints."},{"type":"subheading","content":"VOH (Output High Voltage)"},{"type":"paragraph","content":"When Vin = 0 (or Vin < VTH,driver), the driver is cut off (zero current), so no current flows through the load either, meaning there is no IR-type drop across the load device. However, since the load itself is a MOSFET rather than an ideal wire, the output cannot rise all the way to VDD if the load's own gate-source condition would turn it off first; for a standard enhancement-load configuration with the load gate tied to VDD, VOH is limited to VOH = VDD - VTH,load (the output rises until the load's own VGS = VDD - Vout falls to VTH,load, at which point the load itself shuts off, clamping the maximum output voltage) - this VOH < VDD 'threshold drop' penalty is one of the well-known disadvantages of enhancement-load NMOS logic relative to CMOS."},{"type":"subheading","content":"VOL (Output Low Voltage)"},{"type":"paragraph","content":"When Vin = VDD (driver fully on, strongly driven into triode region since Vout is pulled low), VOL is found by equating the driver's triode current to the load's saturation current: (k_driver)*[(VDD-VTH,driver)*VOL - VOL^2/2] = (k_load/2)*(VDD-VOL-VTH,load)^2. Since VOL is small, the VOL^2/2 term is often neglected for a first approximation, giving VOL ≈ (k_load/k_driver)*(VDD-VTH,load)^2 / [2*(VDD-VTH,driver)], showing that VOL is minimized (a better logic-low level) by making the driver transistor's k (aspect ratio) much larger than the load's, i.e., a large driver-to-load ratio, the same 'ratioed logic' design principle used in NMOS-pull-up-resistor inverters."},{"type":"subheading","content":"VIL and VIH (Input Low and High Thresholds)"},{"type":"paragraph","content":"VIL and VIH are defined as the two points on the VTC where the slope dVout/dVin = -1 (unity gain points), found by differentiating the region-appropriate KCL current-balance equation with respect to Vin and setting the derivative to -1. VIL corresponds to the point where the driver just enters saturation from cutoff (a small increase in Vin from VIL causes Vout to begin dropping with unity or greater gain), while VIH corresponds to the point where the driver transitions from saturation into the triode region as Vin increases further. Solving the unity-gain-slope condition in each region yields closed-form expressions for VIL and VIH in terms of VDD, VTH,driver, VTH,load, and the k_load/k_driver ratio; the exact algebra is lengthy, but the essential result is that both VIL and VIH move to higher values as the driver-to-load ratio increases, widening the noise margins on the '0' side while narrowing them somewhat on the '1' side, illustrating the fundamental design trade-off in ratioed NMOS logic between VOL, noise margins, and static power dissipation (since current flows continuously through the series driver-load stack whenever the driver is on)."},{"type":"subheading","content":"CMOS Realization of y = A + B'C"},{"type":"paragraph","content":"The complement of the target function is y' = (A + B'C)' = A'.(B'C)' = A'.(B+C'). The pull-down network (NMOS, active when y=0, i.e. implements the condition y'=1 conducting a path to ground) is therefore built as a series connection of one NMOS transistor gated by A' with a parallel combination of two NMOS transistors gated by B and C' respectively - since y' = A'.(B+C'), series represents AND and parallel represents OR in the switch-network sense. The pull-up network (PMOS) is the dual of the pull-down network: wherever the PDN has a series connection the PUN has a parallel connection and vice versa, so the PUN consists of a parallel combination of one PMOS gated by A' with a series combination of two PMOS gated by B and C'. Note that since the literals available for direct gating are A, B, and C (not their primed complements, unless additional inverters are used), a small preceding inverter stage generating A' and C' is required, or equivalently the transistors gated by A' and C' are driven by dedicated inverter outputs feeding into the main gate structure - the composite circuit then correctly implements y = A + B'C at the output node where PDN and PUN meet."},{"type":"paragraph","content":"It is worth contrasting the enhancement-load NMOS inverter analyzed above with the alternative depletion-load NMOS inverter, in which the load transistor is a depletion-mode device (having a negative threshold voltage, so it conducts even at VGS=0) with its gate tied directly to its own source rather than to VDD. This depletion-load configuration avoids the VOH = VDD - VTH,load penalty entirely, since the load's gate-source voltage remains fixed at zero regardless of Vout, allowing the load to continue supplying current (and hence the output to be pulled essentially all the way to VDD) even as Vout approaches VDD - this was historically the preferred NMOS logic configuration wherever depletion-mode implantation was available in the process, precisely because it eliminates the enhancement-load inverter's VOH degradation."},{"type":"paragraph","content":"Beyond the DC transfer characteristic, the driver-to-load ratio (often denoted kR = k_driver/k_load) is the single most important design parameter of any ratioed NMOS inverter, since it simultaneously determines VOL, the noise margins, and the static power dissipation of the gate. A larger kR improves VOL (a lower, better logic-low level) and widens the low-side noise margin, but since current flows continuously through the driver-load series path whenever the driver is on (unlike in CMOS, where no static current path exists in steady state), a larger kR driver transistor also draws more static current and hence dissipates more static power - this fundamental static-power penalty, entirely absent in complementary CMOS logic, is precisely why NMOS-only logic families were superseded by CMOS as power consumption became an increasingly dominant concern in VLSI design from the 1980s onward."},{"type":"paragraph","content":"Regarding the CMOS realization of y = A + B'C, it should be further noted that if the design constraint requires the true, non-inverted uncomplemented literals B and C (rather than needing separate inverters to generate B' and C') to be more directly usable in the switch network, an equivalent AOI-gate convention treats the NMOS pull-down network's transistors as being gated directly by the true literals appearing in the SUM-OF-PRODUCTS expression for the complementary function, with the overall gate naturally producing an inverted output at the shared PDN/PUN node - in that convention, an OAI (OR-AND-INVERT) or AOI structure directly yields y' rather than y, and a single explicit inverter stage following the AOI gate recovers the true, non-inverted function y=A+B'C, a common and area-efficient practice throughout static CMOS logic design since compound AOI/OAI gates realize complex Boolean functions with fewer total transistors than would be needed by cascading separate elementary NAND/NOR/inverter gates."}]}},{"id":"vlsi-design-2019-7E7084-u2-q2or","number":4,"marks":16,"tags":["Unit II","Q.2 OR"],"text":[{"type":"paragraph","content":"2. (a) Draw and explain the working of Transmission gate (TG). Use it for 2x1 CMOS multiplexer. [8]"},{"type":"paragraph","content":"(b) What is transistor sizing? Design a y=ABC CMOS logic such that its equivalent (D/L) of pull up section is 90 and pull down section is 30. [8]"}],"answer":{"explanation":[{"type":"subheading","content":"Transmission Gate Operation, 2x1 CMOS Multiplexer, and Transistor Sizing for y=ABC"},{"type":"svg","content":"","alt":"Transmission gate schematic showing parallel NMOS and PMOS transistors with complementary control signals C and C-bar"},{"type":"paragraph","content":"A transmission gate (TG) is a bidirectional CMOS switch formed by connecting an NMOS and a PMOS transistor in parallel between the same input and output nodes, with their gates driven by complementary control signals (C on the NMOS gate, C' on the PMOS gate). When C=1 (C'=0), both transistors turn on simultaneously and the gate conducts, passing the input signal to the output with low resistance across the full voltage range; when C=0 (C'=1), both transistors turn off and the gate presents a high-impedance open circuit. The key advantage of using both an NMOS and a PMOS in parallel, rather than a single pass transistor, is that it eliminates the threshold-voltage-drop problem: a lone NMOS pass transistor conducts a strong '0' but only a degraded 'weak 1' (up to VDD - VTH,n), while a lone PMOS passes a strong '1' but a degraded '0' - the parallel combination ensures that for any input level, at least one of the two transistors is fully on, so the transmission gate passes both logic levels essentially rail-to-rail without degradation."},{"type":"paragraph","content":"A 2x1 CMOS multiplexer selects between two inputs, A and B, based on a select signal S, producing output Y = S'.A + S.B. Using transmission gates, this is realized with two TGs: the first TG has its NMOS gated by S' and PMOS gated by S, connecting input A to the output Y when S=0; the second TG has its NMOS gated by S and PMOS gated by S', connecting input B to the output Y when S=1. Both TG outputs are tied together at the common output node Y. Since exactly one of the two transmission gates is conducting at any time (determined by S), the output always reflects the selected input with minimal voltage degradation, and this TG-based multiplexer implementation requires only 4 transistors total (2 per gate) compared to a full static CMOS AOI-based multiplexer implementation, which would require considerably more transistors, making the transmission-gate approach attractive for area- and power-efficient multiplexer design."},{"type":"subheading","content":"Transistor Sizing for y = ABC"},{"type":"paragraph","content":"Transistor sizing refers to choosing the width-to-length (W/L, or equivalently D/L in this notation) ratio of each transistor in a CMOS gate so that the gate achieves a desired current-drive strength, matching or exceeding that of a reference minimum-sized inverter, ensuring balanced rise and fall delays and adequate noise margins. For a series-connected stack of n transistors of the same type, each individual transistor must be sized n times larger than the equivalent single-transistor (D/L) to compensate for the increased effective channel length (equivalently, increased resistance) of n series-connected devices, since n series transistors of individual (D/L) = n*(D/L)_eq present a combined series (D/L) of (D/L)_eq."},{"type":"paragraph","content":"For y = ABC realized via a 3-input NAND-based structure (y = ABC requires a pull-down network implementing y'=(ABC)' = A'+B'+C', i.e., a parallel PDN, and a pull-up network implementing the series-connected dual for the true output after an inverting stage, or here more directly as requested, we size the pull-down as a series-A,B,C NMOS stack (implementing the AND condition for the non-inverted y-sensing network before a following inverter) and the pull-up as a parallel PMOS stack): the question specifies the combined equivalent (D/L) of the pull-up (parallel PMOS) section must be 90 and the pull-down (series NMOS) section must be 30."},{"type":"math","content":"\\text{Series NMOS: } (D/L)_{eq} = \\frac{(D/L)_{individual}}{n} = 30 \\Rightarrow (D/L)_{individual} = 30 \\times 3 = 90 \\text{ each}"},{"type":"math","content":"\\text{Parallel PMOS: } (D/L)_{eq} = n \\times (D/L)_{individual} = 90 \\Rightarrow (D/L)_{individual} = 90 / 3 = 30 \\text{ each}"},{"type":"paragraph","content":"Therefore, each of the three series NMOS transistors (implementing A, B, C in series in the pull-down path) must individually be sized at (D/L) = 90, since three series transistors of individual ratio 90 combine to an equivalent series (D/L) of 90/3 = 30 as required. Each of the three parallel PMOS transistors (implementing A', B', C' in parallel in the pull-up path, or A, B, C in parallel depending on the exact gate polarity convention used) must individually be sized at (D/L) = 30, since three parallel transistors of individual ratio 30 combine to an equivalent parallel (D/L) of 3*30 = 90 as required. This sizing correctly compensates for the inherent strength-degrading effect of stacking transistors in series (which multiplies effective resistance) versus the strength-enhancing effect of placing transistors in parallel (which divides effective resistance), ensuring the composite 3-input gate matches the drive strength targets specified for both the pull-up and pull-down networks."},{"type":"paragraph","content":"It is also useful to note the practical limitation of transmission gates: while a TG passes both logic levels without the threshold-voltage degradation of a lone pass transistor, it still introduces a finite, voltage-dependent series resistance (arising from the parallel combination of the NMOS and PMOS channel resistances, which varies somewhat with the input signal level since the two transistors' individual on-resistances are complementary functions of the signal voltage). This resistance, combined with the capacitive loading of subsequent circuit stages, introduces an RC propagation delay through each transmission gate, which is why long chains of cascaded transmission gates (as might arise in a large multiplexer tree or programmable interconnect fabric) can accumulate significant delay and typically require periodic buffering (restoring inverter stages) to maintain adequate signal integrity and speed across a large multiplexer or routing structure."},{"type":"paragraph","content":"The general transistor-sizing principle demonstrated for y=ABC extends directly to arbitrarily complex series-parallel switch networks: for any series-connected group of n transistors, each individual transistor must be widened by a factor of n relative to the network's target equivalent (D/L), since n series resistances of value R each combine to a total series resistance of n*R (so each individual transistor's resistance, and hence its (D/L), must be reduced/increased by the reciprocal factor n to compensate). Conversely, for any parallel-connected group of n transistors, each individual transistor's (D/L) must be reduced (narrowed) by the same factor n relative to the network's target equivalent (D/L), since n parallel resistances of value R each combine to a total parallel resistance of R/n. This sizing methodology, applied recursively to arbitrarily nested series-parallel PDN/PUN switch-network trees, is the standard technique used throughout static CMOS gate design (and is implemented automatically within modern standard-cell characterization and custom transistor-sizing CAD tools) to ensure every logic gate in a design meets its required drive-strength and balanced rise/fall-delay specifications regardless of the specific Boolean function or fan-in it implements."}]}},{"id":"vlsi-design-2019-7E7084-u3-q3","number":5,"marks":16,"tags":["Unit III","Q.3"],"text":[{"type":"paragraph","content":"3. (a) Draw following CMOS Ckt - (i) y=A+BC+D (ii) y=A'+B'C' [4+4=8]"},{"type":"paragraph","content":"(b) Draw the layout of y=AB+CDE CMOS ckt use Euler path in it. [8]"}],"answer":{"explanation":[{"type":"subheading","content":"CMOS Circuits for y=A+BC+D and y=A'+B'C', and Euler-Path Layout for y=AB+CDE"},{"type":"paragraph","content":"For y = A + BC + D: the complement is y' = (A+BC+D)' = A'.(BC)'.D' = A'.(B'+C').D'. The pull-down network (NMOS) therefore implements y'=1 as a series connection of A', D', and a parallel combination of B' and C' (all three series-connected blocks in series: A', then the parallel(B',C') block, then D'). The pull-up network (PMOS) is the series-parallel dual: a parallel connection of A', D', and a series combination of B' and C'. As with the earlier AOI structures, since the switch-level literals used are the complements A', B', C', D', either dedicated small inverters generate these complements from the true inputs, or (more commonly in practice) the gate is designed so the NMOS and PMOS device gates are directly driven by the true signals A, B, C, D with the network topology itself (not literal inversion) implementing the required logic - the standard convention is that for an AOI (AND-OR-INVERT) gate of this form, NMOS gates are driven directly by A, B, C, D (not their complements), with the series/parallel arrangement of the PDN mirroring the AND/OR structure of the terms being summed, and the output naturally emerges inverted (giving y' at the output, requiring a following inverter stage to recover true y if needed)."},{"type":"paragraph","content":"For y' = A' + B'C' (i.e., y = A'+B'C' is itself the function required, which is already in a convenient AOI-inverted form): treating y=A'+B'C' as the direct output of an AOI gate, its complement is y' = (A'+B'C')' = A.(B'C')' = A.(B+C). The pull-down network implementing y'=1 is series A with a parallel combination of B and C. The pull-up network (dual) is parallel A with a series combination of B and C. This is a standard 3-input AOI21-type gate structure (one literal ORed with the AND of two others, then inverted), realized with 3 NMOS and 3 PMOS transistors total."},{"type":"subheading","content":"Euler Path Layout for y = AB + CDE"},{"type":"svg","content":"","alt":"Stick diagram layout for CMOS gate implementing y=AB+CDE using a single continuous Euler path diffusion strip across five polysilicon gates"},{"type":"paragraph","content":"The Euler-path layout technique aims to find a single ordering of the input gate signals (a permutation of A, B, C, D, E in this case) such that a single, uninterrupted diffusion strip can be drawn through all the transistors of both the NMOS pull-down network and the PMOS pull-up network, without needing to lift the diffusion (i.e., without requiring any break/gap in the diffusion strip that would otherwise force separate diffusion islands connected by metal, wasting layout area). For y = AB+CDE, the complement is y' = (AB+CDE)' = (AB)'.(CDE)' = (A'+B').(C'+D'+E'). The PDN structure corresponding to this expression is a series-parallel network: A and B in series (implementing the AB product) in parallel with C, D, E all in series (implementing the CDE product), the two parallel branches joined at both the top (to output) and bottom (to ground)."},{"type":"paragraph","content":"Representing this network as a graph (nodes = circuit junction points, edges = transistors labeled by their gate signal) and searching for an Euler path (a path traversing every edge exactly once) reveals that the gate ordering A-B-C-D-E (or an equivalent ordering that keeps the two series-connected groups AB and CDE contiguous and adjacent, such as A-B then continuing to C-D-E) permits a single continuous diffusion path threading through all five transistors of the PDN in sequence, since the AB branch and CDE branch share common top and bottom junction nodes that allow the path to continue from the end of one branch's transistors directly into the start of the other's without a diffusion break. The dual PUN (PMOS network: A,B in parallel joined in series with the parallel combination... more precisely the dual of the PDN structure, which for series-parallel dual networks is parallel(A,B) in series with parallel(C,D,E)) uses the identical gate ordering A-B-C-D-E stacked directly above the NMOS row in the standard two-row (NMOS row, PMOS row) stick-diagram layout convention, since a valid Euler-path ordering for the PDN is simultaneously valid for its dual PUN. This shared single gate ordering across both rows is precisely what allows the polysilicon gate strips to run as simple continuous vertical lines crossing both the NMOS and PMOS diffusion rows without any jogs, producing the most compact possible layout for this 5-transistor-per-network AOI gate."},{"type":"paragraph","content":"It is worth noting that the choice between implementing a complex Boolean expression as a single compound AOI/OAI gate (as done for both y=A+BC+D and y=A'+B'C' above) versus decomposing it into multiple cascaded elementary gates (inverters, NAND2, NOR2, etc.) represents a fundamental trade-off in static CMOS design: the compound single-gate realization uses fewer total transistors and incurs only a single gate-delay's worth of propagation delay (rather than accumulating delay across multiple cascaded stages), but produces a PDN/PUN network with more series-stacked transistors than a simple 2-input gate, and each additional series-stacked transistor adds resistance that slows the gate's own switching speed - so beyond a certain fan-in and stack-depth (commonly 3 to 4 series transistors in practice), the compound-gate approach's single-stage-delay advantage can be outweighed by its own increased internal series resistance, motivating designers to decompose very complex expressions into multiple simpler cascaded stages instead."},{"type":"paragraph","content":"Regarding the Euler-path layout technique more broadly, it is important to recognize that not every arbitrary series-parallel switch network necessarily admits a valid Euler path using a single common gate ordering for both its NMOS and PMOS networks; when no such common ordering exists, the layout must either accept one or more diffusion breaks (requiring additional metal-to-diffusion contacts and hence extra layout area to bridge the discontinuous diffusion regions), or the designer may restructure the underlying Boolean expression itself (exploiting associativity, commutativity, or alternative factorizations of the same logic function) specifically to arrive at a switch-network topology that does admit a compact, single-path Euler ordering - this consideration is why compact standard-cell layout design for complex AOI/OAI gates in real commercial cell libraries often involves iterating over multiple algebraically-equivalent factorizations of the same target Boolean function purely to find the one yielding the most compact, Euler-path-compatible transistor layout."},{"type":"paragraph","content":"For the specific 5-transistor y=AB+CDE example, the practical layout benefit of achieving a valid Euler path is significant: without it, the two branches (the AB series pair and the CDE series triple) would need to be laid out as two physically separate diffusion strips joined only by metal interconnect at the shared top (output) and bottom (ground/VDD) nodes, consuming additional metal routing area and at least one extra diffusion-to-metal contact per branch junction; with the valid Euler-path ordering found above, however, the entire 5-transistor network is realized as one single, unbroken diffusion strip with polysilicon gates crossing it at the five ordered positions, minimizing both the diffusion-region area and the number of contacts required, which is precisely the layout-density benefit that makes Euler-path-based transistor ordering a standard, systematically applied technique in real full-custom and standard-cell CMOS layout methodology."}]}},{"id":"vlsi-design-2019-7E7084-u3-q3or","number":6,"marks":16,"tags":["Unit III","Q.3 OR"],"text":[{"type":"paragraph","content":"3. (a) What is Latch up Problem? How it can be avoided in CMOS ckts? [8]"},{"type":"paragraph","content":"(b) State any four DRC rules regarding: (i) Contact size (ii) Metal to Metal line separation (iii) Poly width and (iv) Separation between pdiff and Ndiff. [4x2=8]"}],"answer":{"explanation":[{"type":"subheading","content":"Latch-Up Problem in CMOS and Design Rule Checks (DRC)"},{"type":"svg","content":"","alt":"Cross-section illustrating the parasitic PNP and NPN bipolar transistors formed within N-well CMOS structure that create a latch-up thyristor"},{"type":"paragraph","content":"Latch-up is a parasitic failure mode inherent to bulk CMOS technology, arising because the standard N-well CMOS fabrication process inherently creates two parasitic bipolar junction transistors embedded within the structure: a vertical PNP transistor (formed by the PMOS source/drain P+ diffusion, the N-well, and the P-substrate) and a lateral NPN transistor (formed by the NMOS source/drain N+ diffusion, the P-substrate, and the N-well). Critically, the collector of each parasitic BJT is connected to the base of the other, and together with the well and substrate resistances (Rwell and Rsub, representing the finite resistance of the N-well and P-substrate regions between the contacts and the active device regions), this cross-coupled pair forms a parasitic PNPN structure that is topologically identical to a silicon-controlled rectifier (SCR) or thyristor."},{"type":"paragraph","content":"Under normal operating conditions, this parasitic thyristor remains off because the base-emitter junctions of both parasitic BJTs are held reverse- or zero-biased by the well and substrate contacts tying N-well to VDD and P-substrate to ground. However, a sufficiently large transient disturbance - such as input/output voltage overshoot beyond the supply rails, undershoot below ground, ESD (electrostatic discharge) events, or noise injected through the well/substrate resistances - can momentarily forward-bias one of the parasitic base-emitter junctions enough to turn on one of the parasitic BJTs. Because the two parasitic transistors are cross-coupled (each one's collector current feeds the other's base), turning on one triggers regenerative positive feedback that turns the other on as well, and vice versa, causing the parasitic thyristor to 'latch' into a low-impedance, high-current conduction state connecting VDD directly to ground through the chip substrate. This creates a sustained low-resistance short circuit between the power rails that persists even after the triggering disturbance is removed, since the thyristor remains latched by its own internal regenerative feedback as long as sufficient holding current continues to flow - the resulting high current typically causes localized heating severe enough to permanently destroy the chip (via metal trace fusing or junction burnout) unless the power supply is cut immediately."},{"type":"subheading","content":"Latch-Up Prevention Techniques"},{"type":"list","items":["Guard rings: placing continuous, heavily-doped N+ rings (tied to VDD) around PMOS/N-well regions and P+ rings (tied to ground) around NMOS regions intercepts minority carriers before they can be collected by the parasitic BJT bases, effectively short-circuiting the parasitic base-emitter junctions and preventing them from ever turning on.","Reducing well and substrate resistance: increasing the density of substrate and well contacts (placing many closely-spaced VDD and ground contacts throughout the layout rather than just at the chip periphery) lowers Rwell and Rsub, which directly reduces the voltage drop available to forward-bias the parasitic base-emitter junctions for any given injected current, raising the trigger threshold for latch-up.","Physical spacing: maintaining adequate separation between adjacent NMOS and PMOS devices (and particularly between N-well/P-substrate boundaries and sensitive I/O circuitry) reduces the parasitic bipolar current gain (beta) of the PNPN structure by increasing the effective base width of the parasitic transistors, making regenerative turn-on progressively harder to sustain as spacing increases.","Retrograde wells and epitaxial (epi) substrates: process-level techniques where the doping profile is engineered (retrograde wells have higher doping deep in the well, lower near the surface) or a lightly-doped epitaxial layer is grown on a heavily-doped substrate, both of which reduce the effective resistance paths and parasitic bipolar gains that enable latch-up, providing a more fundamental process-technology defense in addition to layout-level guard-ring and spacing techniques."]},{"type":"subheading","content":"Design Rule Check (DRC) Rules"},{"type":"list","items":["Contact size: contacts (vias connecting metal to diffusion or poly) must meet a minimum size (typically expressed as 2*lambda x 2*lambda in the lambda-based design rule system) to guarantee reliable, sufficiently low-resistance electrical connection and adequate process manufacturability margin against contact-etch variability.","Metal-to-metal line separation: adjacent metal interconnect lines on the same layer must maintain a minimum spacing (commonly 3*lambda) to prevent unintended short circuits due to lithographic and etch process variation, while also limiting parasitic capacitive coupling between adjacent signal lines.","Poly width: polysilicon gate lines must maintain a minimum width (typically 2*lambda) since the poly width directly sets the transistor channel length, and any width variation from process limitations directly translates into transistor performance (drive current, threshold voltage via short-channel effects) variation across the chip.","Separation between p-diffusion and n-diffusion: a minimum spacing (commonly 10-12*lambda) must be maintained between adjacent P-diffusion and N-diffusion regions (such as between an NMOS source/drain and a neighboring PMOS source/drain) both to accommodate the N-well boundary and guard-ring structures physically fitting between them, and to maintain adequate latch-up immunity by keeping the parasitic bipolar structures discussed above sufficiently far apart."]},{"type":"paragraph","content":"Beyond the layout-level and process-level prevention techniques already described, it is also worth noting the circuit-design-level precautions commonly taken specifically at input/output pad circuitry, which is the most latch-up-vulnerable region of any chip since I/O pads are directly exposed to external voltage transients, overshoot, and ESD events from outside the chip package. Dedicated ESD protection structures (clamping diodes to VDD and ground, along with series resistance to limit peak injected current) are placed at every I/O pad specifically to prevent external transients from ever reaching a magnitude capable of forward-biasing the parasitic base-emitter junctions of the latch-up thyristor structure in the first place, complementing the guard-ring and spacing techniques used more broadly across the internal core logic of the chip."},{"type":"paragraph","content":"The design rule check (DRC) process itself, within which the four specific rules discussed above (contact size, metal-to-metal spacing, poly width, and p-diffusion-to-n-diffusion separation) are just a small representative sample, is run as an automated verification step against the complete physical layout database (typically in GDSII format) prior to mask generation and fabrication, checking every layer and every layer-to-layer relationship in the design against the foundry's complete design rule manual (which may contain many hundreds of individual geometric rules for an advanced process node). A layout that fails any DRC rule is flagged for correction before tape-out, since a DRC violation represents a layout geometry that the target fabrication process cannot reliably manufacture, risking either complete circuit failure (e.g., an unintended short from insufficient metal spacing) or reduced yield and reliability (e.g., a contact that is undersized and hence prone to open-circuit failure from process-induced etch variation) if left uncorrected."},{"type":"paragraph","content":"Because DRC rules are expressed in the lambda-based scalable design rule system (where lambda is defined as half the minimum drawn feature size for a given process generation), the same set of DRC rules, expressed purely as lambda-multiples as illustrated by the four examples above, can in principle be reused across multiple process generations simply by redefining the numerical value of lambda for each new, smaller process node, though in practice modern sub-micron and deep-submicron processes increasingly require additional micron-based absolute design rules (rather than pure lambda-scaling) to correctly capture non-linear scaling effects and process-specific manufacturing constraints that do not scale simply with feature size."}]}},{"id":"vlsi-design-2019-7E7084-u4-q4","number":7,"marks":16,"tags":["Unit IV","Q.4"],"text":[{"type":"paragraph","content":"4. Draw and explain any two logic Ckt from - (i) NORA logic (ii) DRAM (iii) DOMINO logic (iv) NP logic. [2x8=16]"}],"answer":{"explanation":[{"type":"subheading","content":"NORA Logic and DRAM (Dynamic Random Access Memory)"},{"type":"svg","content":"","alt":"NORA CMOS logic diagram showing alternating N-block and P-block dynamic logic stages connected by static or dynamic buffers"},{"type":"paragraph","content":"NORA (NO RAce) logic is a clocked dynamic CMOS logic family designed to allow direct cascading of alternating dynamic logic stages without inserting static buffer/inverter stages between every pair of dynamic gates, which conventional domino logic requires. NORA achieves this by alternating between two types of dynamic blocks: N-blocks, which use an NMOS pull-down evaluation network (precharged high via a PMOS precharge transistor, similar to standard domino logic), and P-blocks, which use a PMOS pull-up evaluation network (precharged low via an NMOS precharge transistor, i.e. the logical dual structure). Because N-blocks and P-blocks precharge to opposite logic levels and evaluate with opposite clock-phase relationships, an N-block's dynamically-evaluated output (which only ever falls monotonically during evaluation, just as in domino logic) can directly drive the gate inputs of a following P-block without an intervening static inverter, since the P-block's PMOS pull-up network correctly interprets a monotonically-falling input as expected."},{"type":"paragraph","content":"This alternating N-block/P-block cascading eliminates the mandatory static-inverter overhead of domino logic between every stage, reducing both silicon area and the additional delay/power that static buffers would introduce, at the cost of requiring careful, disciplined design of alternating clock-phase relationships and gate ordering across the pipeline to maintain the correct monotonicity assumptions throughout the cascade - a design discipline that gives the logic family its name (avoiding 'races' between the precharge and evaluate transitions of adjacent stages that could otherwise cause incorrect intermediate glitches to propagate)."},{"type":"subheading","content":"DRAM (Dynamic Random Access Memory)"},{"type":"svg","content":"","alt":"Single transistor single capacitor DRAM memory cell with access transistor gated by word line and storage capacitor"},{"type":"paragraph","content":"DRAM stores each bit of data as electric charge on a small storage capacitor Cs, accessed through a single NMOS access transistor whose gate is connected to the word line and whose drain/source path connects the storage capacitor to the bit line. When the word line is asserted, the access transistor turns on, connecting the storage capacitor to the bit line, allowing either a write operation (the bit-line driver forces the capacitor to charge or discharge to the desired logic level) or a read operation (the small charge stored on Cs is shared with the much larger bit-line parasitic capacitance Cbl, producing a small voltage perturbation on the bit line that a sense amplifier detects and amplifies to a full logic level)."},{"type":"paragraph","content":"Because the storage capacitor Cs inevitably leaks charge over time (through the access transistor's subthreshold leakage current and junction leakage at the storage node), DRAM requires periodic refresh operations - every row must be read out and rewritten at full strength at a regular interval (typically every few tens of milliseconds) before the stored charge decays enough to be misread, which is the defining characteristic that makes DRAM 'dynamic' (as opposed to SRAM, which holds its stored state indefinitely via cross-coupled feedback as long as power is supplied, requiring no refresh). This need for refresh circuitry adds design complexity and a small periodic power/bandwidth overhead, but is more than compensated for by DRAM's dramatically smaller per-bit cell area (a single transistor plus a single capacitor, versus SRAM's six transistors per bit), which is precisely why DRAM is the technology of choice for high-density main memory, while SRAM (faster, no refresh needed, but larger and more power-hungry per bit) is reserved for smaller, speed-critical applications such as processor cache memory."},{"type":"paragraph","content":"Comparing NORA logic and DRAM as two distinct VLSI logic/memory circuit techniques highlights the breadth of design considerations spanning combinational-logic-speed optimization versus data-storage-density optimization within the same underlying CMOS technology. NORA logic exemplifies the broader family of clocked dynamic logic circuits (which also includes domino logic, NP-domino/zipper CMOS, and cascode voltage switch logic), all of which trade the unconditional logical robustness and zero static power consumption of fully static CMOS gates for higher switching speed and reduced transistor count per logic function, at the cost of requiring careful multi-phase clocking discipline, susceptibility to charge-sharing and leakage-induced dynamic-node corruption if evaluation is delayed too long, and reduced noise immunity compared to static gates."},{"type":"paragraph","content":"DRAM, by contrast, exemplifies the memory-density-optimized side of VLSI design, where a single transistor plus capacitor cell achieves roughly one-sixth the area of an equivalent SRAM cell, at the cost of requiring not only periodic refresh circuitry but also a considerably more complex sense-amplifier and precharge circuit design to reliably detect and restore the very small charge-sharing voltage signal produced on the bit line during a read access (since the storage capacitor is deliberately made as small as possible to maximize density, while the bit-line parasitic capacitance it must share charge with is comparatively much larger, producing bit-line voltage swings during a DRAM read access typically in the range of only a few hundred millivolts, requiring highly sensitive, carefully balanced differential sense amplifiers to correctly resolve)."},{"type":"paragraph","content":"Both NORA logic and DRAM ultimately illustrate a recurring theme throughout VLSI circuit design: exploiting the temporary charge-storage capability of a node's own parasitic or dedicated capacitance (the dynamic evaluation node in NORA/domino logic, or the explicit storage capacitor in a DRAM cell) to reduce transistor count and/or improve switching speed relative to a fully static, continuously-driven circuit alternative, while accepting the added complexity of managing that stored charge's inevitable, finite retention time through careful timing discipline (for dynamic logic) or explicit periodic refresh (for DRAM) - a trade-off pattern that recurs throughout digital IC design wherever area, speed, or power constraints motivate designers to depart from the simplicity of fully static, continuously-restoring circuit topologies."},{"type":"paragraph","content":"Consequently, a circuit designer choosing between dynamic logic families like NORA and memory technologies like DRAM is never selecting one universally superior approach, but rather matching the specific circuit technique to the specific design goal (raw combinational switching speed for NORA-style dynamic logic, versus maximum bit-storage density for DRAM), a decision-making pattern that recurs throughout the entire discipline of VLSI design."},{"type":"paragraph","content":"This same design-technique-selection principle extends naturally to the two remaining logic families mentioned in the question, DOMINO logic and NP/Zipper CMOS, each occupying a further distinct point along the speed-versus-robustness design spectrum available to the VLSI circuit designer."},{"type":"paragraph","content":"Recognizing these distinctions is what allows an experienced VLSI designer to select the most appropriate circuit family for each block of a larger chip design, rather than defaulting to a single logic style throughout."}]}},{"id":"vlsi-design-2019-7E7084-u5-q5","number":8,"marks":16,"tags":["Unit V","Q.5"],"text":[{"type":"paragraph","content":"5. Write short note on any two: (i) VHDL code (ii) FPGA (iii) Custom design (iv) ASIC design. [2x8=16]"}],"answer":{"explanation":[{"type":"subheading","content":"VHDL Code and FPGA (Field Programmable Gate Array)"},{"type":"paragraph","content":"VHDL (VHSIC Hardware Description Language, where VHSIC stands for Very High Speed Integrated Circuit) is a standardized hardware description language (IEEE 1076) used to describe, simulate, and synthesize digital electronic circuits and systems, ranging from simple combinational gates to complete processors. A VHDL design is organized around the entity/architecture pairing: the entity declaration defines the external interface of a design unit (its input and output ports and their types), while one or more architecture bodies associated with that entity describe its internal behavior, either structurally (as an interconnection of component instances), behaviorally (as an algorithmic description using processes, signal assignments, if/case statements, closely resembling ordinary sequential programming), or as a dataflow description (concurrent signal assignment statements)."},{"type":"code-block","language":"vhdl","content":"library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nentity and_gate is\n Port ( a : in STD_LOGIC;\n b : in STD_LOGIC;\n y : out STD_LOGIC);\nend and_gate;\n\narchitecture Behavioral of and_gate is\nbegin\n y <= a and b;\nend Behavioral;"},{"type":"paragraph","content":"This short example illustrates the two-part entity/architecture structure for a simple 2-input AND gate: the entity block declares the interface (two STD_LOGIC input ports a and b, and one STD_LOGIC output port y), while the architecture block (named Behavioral here, though any identifier may be used) provides the actual logic implementation, in this case using a single concurrent dataflow-style signal assignment. Once written, such VHDL code can be simulated (to verify correct logical behavior against a testbench, before committing to hardware) and subsequently synthesized (translated by synthesis tools into an actual gate-level netlist targeting either an FPGA's programmable logic fabric or a full-custom/ASIC standard-cell library), which is precisely why VHDL has become the dominant language (alongside Verilog) for describing digital hardware throughout the modern chip design industry, spanning simple glue logic up to full microprocessor designs."},{"type":"subheading","content":"FPGA (Field Programmable Gate Array)"},{"type":"paragraph","content":"An FPGA is a reconfigurable semiconductor device containing a large array of programmable logic blocks (commonly called Configurable Logic Blocks or CLBs, each internally built from one or more Look-Up Tables (LUTs) capable of implementing arbitrary combinational logic functions of a small number of inputs, plus flip-flops for sequential storage), a rich programmable interconnect fabric of wires and configurable switch matrices allowing arbitrary routing between logic blocks, and dedicated I/O blocks at the periphery for interfacing with external signals. Unlike an ASIC (Application-Specific Integrated Circuit), whose logic function is permanently fixed at fabrication time by the specific mask set used, an FPGA's logic function is determined entirely by a configuration bitstream loaded into on-chip configuration memory (typically SRAM-based, meaning the configuration must be reloaded every power-up, though some FPGA families use non-volatile flash or antifuse configuration memory instead), which programs the LUT contents and interconnect switch settings to realize whatever specific digital circuit the designer has synthesized."},{"type":"paragraph","content":"This reconfigurability gives FPGAs their key advantages of rapid design turnaround (no fabrication lead time - a new or corrected design can be tested within minutes of synthesis completing, versus the weeks-to-months fabrication cycle and enormous non-recurring engineering cost of a new ASIC mask set) and field-upgradability (a deployed FPGA-based product can have its function changed or bug-fixed by simply loading a new configuration bitstream), at the cost of lower maximum clock speed, higher per-unit cost at high production volumes, and higher power consumption per logic function compared to a full-custom ASIC implementing the identical function, since FPGAs must include substantial programmable-interconnect and configuration-memory overhead not needed in a fixed, hardwired ASIC - this fundamental FPGA-versus-ASIC trade-off (flexibility and fast turnaround versus raw performance and per-unit cost at scale) is precisely why FPGAs are favored for prototyping, low-to-medium production volumes, and designs requiring post-deployment reconfigurability, while ASICs remain favored for extremely high production volumes where per-unit cost and maximum performance dominate the design decision."},{"type":"paragraph","content":"Custom design and ASIC (Application-Specific Integrated Circuit) design represent the opposite end of the design-methodology spectrum from FPGA-based implementation discussed above. In a full-custom design flow, every transistor's size, placement, and interconnect routing is individually hand-crafted (or at minimum, hand-tuned following automated initial placement) by the circuit designer to achieve the maximum possible area efficiency, speed, and power efficiency for a specific target function - this labor-intensive approach is typically reserved for the most performance-critical or highest-volume circuit blocks (such as microprocessor datapath elements, high-speed SRAM/cache arrays, or standard-cell library elements themselves) where the substantial engineering effort is justified by the resulting silicon area, speed, or power advantage multiplied across enormous production volumes."},{"type":"paragraph","content":"ASIC design, more broadly, refers to any integrated circuit designed and fabricated for one specific application (as opposed to a general-purpose, off-the-shelf device such as a standard microprocessor or FPGA usable across many different applications), and encompasses a spectrum of design styles from full-custom (described above) through standard-cell-based design (where the design is composed from a library of pre-characterized, pre-laid-out logic cells - inverters, NAND/NOR gates, flip-flops, and similar - assembled and automatically placed-and-routed by CAD tools based on a synthesized gate-level netlist) to gate-array-based design (where a partially-fabricated wafer containing a regular array of uncommitted transistors is customized only in its final metal interconnect layers, offering faster turnaround and lower non-recurring engineering cost than full-custom or standard-cell design, at some area and performance penalty)."},{"type":"paragraph","content":"The standard ASIC design flow proceeds through several well-defined stages: specification and architectural design, RTL (register-transfer level) coding in a hardware description language such as VHDL or Verilog, functional simulation and verification against the specification, logic synthesis (translating the RTL description into a gate-level netlist using cells from a target standard-cell library, optimized for the specified timing, area, and power constraints), physical design (floorplanning, placement, clock-tree synthesis, and routing), physical verification (design rule checking as discussed in relation to another question in this examination, along with layout-versus-schematic verification), and finally mask generation and fabrication (tape-out). Compared to the FPGA-based approach, ASIC design offers superior performance, power efficiency, and per-unit cost at high production volumes, but at the expense of a far longer design and fabrication turnaround time, substantially higher non-recurring engineering cost (mask sets for advanced process nodes can cost millions of dollars), and the complete inability to modify the design's function after fabrication - trade-offs that make the FPGA-versus-ASIC (or more generally, the reconfigurable-versus-fixed-function) decision one of the most consequential early architectural choices in any digital system design project."},{"type":"paragraph","content":"prompting most modern design teams to adopt FPGA prototyping during early development before committing to a final ASIC implementation for volume production."}]}}],"examYear":2019}],"loading":false,"error":null}}}

Q10VLSI Design

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Answer