Question 1

List the different types of flip flops.

Accepted Answer

The primary categories of flip-flops include SR, JK, D, and T flip-flops, each serving distinct memory functions.

Question 2

Define reflective codes.

Accepted Answer

Reflective codes, such as Gray code, feature mirrored geometric properties where subsequent binary halves reflect the previous halves.

Question 3

State De Morgan's theorem.

Accepted Answer

De Morgan's theorems mathematically prove that the complement of a logical sum equals the product of individual complements, and vice-versa.

Question 4

Convert $(10101101)_2$ -> ( )G

Accepted Answer

Converting binary 10101101 to Gray code requires systematically XORing adjacent binary bits to yield 11111011.

Question 5

Explain race around condition in JK flip flop.

Accepted Answer

A race-around condition occurs in JK flip-flops when prolonged clock pulses cause unpredictable, continuous output toggling.

Question 6

Illustrate Excitation table of SR flip flop.

Accepted Answer

The excitation table of an SR flip-flop details the precise input signals required to achieve specific state transitions.

Question 7

Explain don't care condition.

Accepted Answer

Don't care conditions represent specific input combinations where the resulting output state is completely irrelevant to the system.

Question 8

Show the classification of digital logic families.

Accepted Answer

Digital logic families are primarily classified into Bipolar junction technologies and Unipolar field-effect technologies.

Question 9

Solve (0100 1000. 01111001)XS-3 = ( )10

Accepted Answer

Converting Excess-3 code to decimal requires subtracting binary 0011 from each individual 4-bit encoded nibble.

Question 10

Calculate the value of x. (23)x + (12)x = (101)x

Accepted Answer

Solving the polynomial equation derived from the base representations reveals that the unknown base x is exactly 4.

Question 11

What is multiplexer? Design 4:1 MUX using 2:1 MUX.

Accepted Answer

A detailed exploration of Multiplexer architecture, including its functional definition, and a rigorous step-by-step methodology for constructing a 4:1 Multiplexer utilizing multiple 2:1 Multiplexers in a hierarchical tree topology.

Question 12

Interpret the function $f =$ A+BC in canonical POS form (Product of Sum form).

Accepted Answer

A rigorous mathematical translation of a simplified Boolean expression into its canonical Product of Sums (POS) format, demonstrating the algorithmic expansion of missing variables.

Question 13

Design full adder circuit using half adders.

Accepted Answer

A detailed hardware logic design process demonstrating how to architecturally construct a 3-bit Full Adder circuit utilizing strictly two 2-bit Half Adders and an auxiliary OR gate.

Question 14

Construct CMOS NAND and CMOS NOR gate for two inputs.

Accepted Answer

A deep architectural explanation detailing the complementary transistor topologies strictly required to construct fundamental CMOS NAND and NOR logic gates using PMOS and NMOS networks.

Question 15

Show that i) AB + A'C + BC = AB + A'C ii) AB+A'C = (A+C) (A'+B)

Accepted Answer

A rigorous mathematical proof establishing the validity of the Consensus Theorem, followed by an algebraic demonstration utilizing distributive laws to convert a boolean expression into a factored form.

Question 16

Consider two binary numbers X = 1010100 and $Y =$ 1000011, perform the subtra…

Accepted Answer

A detailed algorithmic execution of binary subtraction operations strictly utilizing the 2's complement methodology, correctly identifying positive results and negative results requiring re-complementation.

Question 17

What are decoders? Implement the following boolean function using 3 to 8 deco…

Accepted Answer

An explanation of decoder architecture, demonstrating how a 3-to-8 line decoder generates canonical minterms, which are subsequently combined via an OR gate to implement a specific Boolean function.

Question 18

Simplify the following boolean function using Quine McCluskey method and veri…

Accepted Answer

A definitive, exhaustive application of the tabular Quine-McCluskey algorithmic methodology to minimize a complex 4-variable Boolean function, strictly verified via K-map analysis.

Question 19

Design a 3-bit synchronous counter using JK flip flops.

Accepted Answer

A highly structured hardware design methodology detailing the step-by-step construction of a 3-bit Synchronous Binary Up-Counter utilizing JK Flip-Flops and combinational excitation logic.

Question 20

Explain the following terms: i) Noise Margin ii) Propagation Delay iii) Fan-I…

Accepted Answer

A comprehensive engineering breakdown of critical digital logic family performance metrics, analyzing electrical tolerances, propagation speeds, driving capabilities, and thermal power limits.

Question 21

Design a 4-bit binary to gray code converter and realize it using logic gates.

Accepted Answer

A complete hardware synthesis of a 4-bit Binary to Gray Code converter, detailing the XOR logic derivation from structural truth tables and its final combinational gate realization.

Question 22

Explain the working of 4-bit serial in parallel-out shift register along with…

Accepted Answer

A deep architectural review of the Serial-In Parallel-Out (SIPO) shift register, explaining internal D-flip-flop data propagation and the exact timing waveform required for parallel extraction.

Digital Electronics