Q14Digital Electronics

Complementary Metal-Oxide-Semiconductor (CMOS) technology completely dominates modern integrated circuit design due to its extraordinarily low static power consumption and massive noise immunity. The core architectural philosophy of CMOS strictly mandates that every single logic gate must be constructed using two perfectly complementary, mutually exclusive structural networks of transistors: a Pull-Up Network (PUN) constructed entirely of p-type MOSFETs (PMOS), connecting the output exclusively to the positive voltage supply ($V_{DD}$), and a Pull-Down Network (PDN) constructed entirely of n-type MOSFETs (NMOS), connecting the output exclusively to Ground ($V_{SS}$). By physical law, PMOS transistors conduct when a logic 0 is applied to their gate, while NMOS transistors conduct when a logic 1 is applied.

1. Two-Input CMOS NAND Gate Construction

The fundamental truth table for a NAND gate demands that the output is pulled LOW (logic 0) if and only if both inputs A AND B are HIGH. In all other scenarios, the output must be forcefully pulled HIGH (logic 1).

NMOS Pull-Down Network (PDN): Because both inputs must be 1 simultaneously to drag the output to ground, the two NMOS transistors must be physically wired in a strict series configuration between the output pin and Ground. Current can only physically flow to ground if both transistors are actively conducting.

PMOS Pull-Up Network (PUN): Due to the strict complementary nature of CMOS, if the NMOS network is in series, the PMOS network must mathematically be in parallel. Two PMOS transistors are wired in parallel between $V_{DD}$ and the output pin. If either input A OR input B is 0, the corresponding PMOS transistor activates, creating a direct, unhindered path from $V_{DD}$ to the output, pulling it HIGH.

2. Two-Input CMOS NOR Gate Construction

Conversely, the truth table for a NOR gate strictly demands that the output is pulled HIGH (logic 1) if and only if both inputs A AND B are LOW. If either input is HIGH, the output must immediately crash to LOW (logic 0).

PMOS Pull-Up Network (PUN): Because both inputs must be 0 simultaneously to pull the output to $V_{DD}$, the two PMOS transistors must be structurally wired in series between $V_{DD}$ and the output. If even one input becomes 1, the series chain is physically severed, and the output cannot reach $V_{DD}$.

NMOS Pull-Down Network (PDN): Maintaining structural complementarity, since the PMOS network is in series, the NMOS network must be wired in parallel. Two NMOS transistors are placed in parallel between the output and Ground. If either input A OR input B becomes 1, the respective NMOS transistor activates, instantly providing a low-resistance path to Ground, pulling the output forcefully LOW. This elegant, dual-network topology completely eliminates static short-circuits.