Q19VLSI Design

Layout Design Rules and Four-Input NAND/NOR Gate Layout

Layout design rules (commonly expressed as lambda-based rules, where lambda is a single process-dependent scaling parameter, allowing the same set of rules to be applied across different fabrication processes simply by changing the value of lambda) specify the minimum allowable dimensions and spacings for each mask layer used in a CMOS fabrication process, ensuring the resulting chip can be reliably manufactured without shorts, opens, or other defects caused by mask misalignment or process variation during fabrication.

• Minimum width rules: specify the smallest allowable width for each layer (polysilicon gate width, typically 2lambda; diffusion width, typically 3lambda; metal width, typically 3*lambda), below which the manufacturing process cannot reliably produce a continuous, defect-free feature.
• Minimum spacing rules: specify the smallest allowable separation between two features on the same layer (or between different layers that must not touch), such as minimum polysilicon-to-polysilicon spacing (2lambda), minimum diffusion-to-diffusion spacing of the same type (3lambda), and minimum spacing between n-diffusion and p-diffusion regions (typically larger, around 10*lambda, to accommodate the required well/tub boundary and prevent latch-up-related issues examined elsewhere in this examination).
• Overlap and enclosure rules: specify the minimum extension of one layer beyond another at a contact or via (for example, metal must overlap a contact cut by at least 1*lambda on all sides, and diffusion or polysilicon must similarly overlap an underlying contact by a minimum amount) to guarantee reliable electrical contact despite mask alignment tolerances.
• Extension rules: specify how far a gate polysilicon line must extend beyond the edge of the diffusion region it crosses (typically 2*lambda), ensuring the transistor's channel is fully defined even under worst-case mask misalignment, preventing an unintended direct short between source and drain diffusion.

A 4-input NAND gate requires 4 PMOS transistors connected in parallel (pull-up network, since the gate must pull the output high whenever ANY one of the four inputs is low) and 4 NMOS transistors connected in series (pull-down network, since the gate must pull the output low only when ALL four inputs are simultaneously high). In the layout, this is realized using two horizontal diffusion strips - a p-diffusion strip (within the n-well) accommodating the 4 parallel PMOS transistors, and an n-diffusion strip accommodating the 4 series NMOS transistors - with four vertical polysilicon gate lines crossing both diffusion strips, each polysilicon line corresponding to one input signal (A, B, C, D) and simultaneously forming the gate of both the corresponding PMOS transistor (in the upper strip) and NMOS transistor (in the lower strip).

For the series-connected NMOS pull-down network specifically, since all 4 NMOS transistors share the property that any two adjacent transistors in the series chain share a common diffusion node, the entire 4-transistor series chain can be laid out as a single continuous n-diffusion strip with the 4 polysilicon gates crossing it at 4 successive points, with metal contacts only needed at the two outer ends (one connecting to the output node, one connecting to ground) plus each internal series node remaining as bare diffusion without needing any contact at all - this Euler-path-style continuous diffusion layout (directly connecting to the Euler path concept examined in relation to another question in this examination) minimizes the diffusion area and eliminates unnecessary contacts compared to a naive layout that separately contacts and wires together four individually-placed transistors.

A 4-input NOR gate has exactly the dual structure: 4 NMOS transistors in parallel (pull-down, output goes low whenever ANY input is high) and 4 PMOS transistors in series (pull-up, output goes high only when ALL inputs are simultaneously low) - the layout mirrors the NAND gate's structure with the series/parallel roles of the two diffusion strips exchanged, again exploiting the continuous-diffusion, minimum-contact layout technique for the series-connected (in this case, PMOS) transistor chain. In both the NAND and NOR layouts, all lambda-based design rules discussed above (minimum diffusion width, minimum polysilicon-to-polysilicon spacing between the four gate lines, minimum contact-to-diffusion-edge spacing at the output and supply/ground contacts, and adequate n-well-to-p-diffusion spacing at the boundary between the two diffusion strips) must be satisfied throughout the layout to ensure the gate can be reliably fabricated.

It is also worth noting the practical trade-off inherent in choosing the value of lambda itself for a given fabrication process: a smaller lambda value allows more aggressive, denser layouts (smaller minimum feature sizes and spacings), directly reducing chip area and cost per die, but requires a correspondingly more advanced (and expensive) fabrication process capable of reliably manufacturing such small features with acceptable yield - this is precisely the parameter that scales down as semiconductor manufacturing technology advances from one process generation (technology node) to the next, and the lambda-based rule system's key practical advantage is that the same set of design rules (expressed purely as multiples of lambda) can be reused essentially unchanged across different process generations, simply substituting the new, smaller lambda value appropriate to the more advanced process, without needing to redesign the entire rule set from scratch for each new technology node.

It is also worth explicitly noting why the n-diffusion-to-p-diffusion spacing rule is typically set considerably larger than same-type diffusion spacing rules: this larger spacing must accommodate the physical n-well (or p-well, depending on process type) boundary itself, which requires a certain minimum width to reliably contain the implanted/diffused well region and to maintain adequate spacing between the well edge and the adjacent diffusion regions of the opposite type, and this well-related spacing requirement is directly connected to preventing the parasitic latch-up phenomenon examined in detail elsewhere in this examination, since an inadequately-spaced n-diffusion-to-p-diffusion boundary increases the risk of triggering the parasitic bipolar PNPN thyristor structure inherent to any bulk CMOS process, making this particular spacing rule one of the most safety-critical design rules in the entire lambda-based rule set for reliable CMOS chip manufacturing.

This complete treatment of lambda-based design rules, together with the specific layout structures for the four-input NAND and NOR gates, illustrates the essential bridge between a circuit's logical/schematic description and its final, physically manufacturable silicon implementation.

This systematic, lambda-scalable design rule methodology, applied consistently across all mask layers in a given fabrication process, is precisely what allows large teams of VLSI designers to independently create different portions of a complex chip with confidence that their individually-designed blocks will integrate correctly and manufacture reliably once combined into the final full-chip layout.