Q18VLSI Design

Dynamic Behavior of MOSFET Transistor

The dynamic (switching) behavior of a MOSFET transistor, as distinct from its static (DC) current-voltage characteristics, is governed by several parasitic capacitances inherent to its physical structure, which must be charged or discharged whenever the transistor's terminal voltages change, and which therefore determine how quickly the device can actually switch states in a real circuit rather than switching instantaneously as an idealized model might suggest.

The gate-to-source capacitance (Cgs) and gate-to-drain capacitance (Cgd) arise from the gate oxide's parallel-plate capacitance between the polysilicon gate electrode and the underlying channel/source/drain regions, and additionally include an overlap component where the gate physically overlaps the source and drain diffusion regions at the edges of the channel due to lateral diffusion during fabrication. The gate-to-drain overlap capacitance Cgd is of particular practical importance because of the Miller effect: in a common-source (inverting) amplifier or logic gate configuration, this capacitance appears between the input and output nodes, and because the output swings in the opposite direction to the input with some voltage gain, the effective input capacitance contributed by Cgd is multiplied by approximately (1+gain), making Cgd's effective loading impact on the driving stage considerably larger than its own nominal physical capacitance value would suggest.

The source-to-body (Csb) and drain-to-body (Cdb) capacitances arise from the reverse-biased PN junctions formed between the n+ source/drain diffusion regions and the p-type substrate (for an NMOS device), behaving as voltage-dependent junction capacitances that decrease somewhat as the reverse bias across them increases (following the standard non-linear junction capacitance-versus-voltage relationship), and additionally including both a bottom-wall component (capacitance per unit area of the diffusion region's bottom surface facing the substrate) and a sidewall (perimeter) component (capacitance per unit length around the diffusion region's edge, often significant for the small diffusion areas typical of modern scaled transistors).

During a switching transition, these parasitic capacitances, together with any external load capacitance (wiring capacitance and the input capacitance of the following logic gate stage), must be charged or discharged through the transistor's own channel resistance (or, more precisely, through the transistor's actual nonlinear current-voltage characteristic in its triode and saturation regions, as examined in relation to the propagation delay derivation elsewhere in this examination) - the time required for this charging/discharging process, rather than any instantaneous switching, is what determines a real MOSFET circuit's actual achievable switching speed and propagation delay, and understanding and correctly modeling this complete set of parasitic capacitances (Cgs, Cgd with its Miller-multiplied effective value, Csb, Cdb, plus external wiring and fan-out load capacitance) is essential for accurate circuit-level timing simulation (SPICE-level modeling) and for informed transistor sizing decisions during VLSI circuit design, since simply assuming an idealized, capacitance-free switch (as might be done for purely logical/functional verification) would give no useful information about the actual achievable operating speed of a real fabricated circuit.

Additionally, the channel charge itself (the mobile inversion-layer charge present when the transistor is ON) must be either supplied (when turning on) or removed (when turning off) through the source and drain terminals, contributing a further dynamic charging effect sometimes modeled as an additional channel charge capacitance partitioned between the source and drain terminals depending on the specific operating region (this channel-charge partitioning, and the associated charge-sharing/clock-feedthrough effects when a transistor switches off while charge is still present in its channel, is of particular practical importance in dynamic and switched-capacitor circuit design, including the domino logic and charge-sharing considerations examined in relation to other questions in this examination) - together, this complete picture of gate-oxide capacitance, junction capacitance, Miller-effect amplification, and channel-charge dynamics constitutes the full dynamic behavior model of a real MOSFET transistor as used in practical VLSI circuit design and simulation.

It is also worth noting the practical circuit-design implications of the Miller-effect-amplified Cgd discussed above: because this effective input capacitance depends on the voltage gain of the stage being driven, a logic gate driving a following inverting stage sees a input capacitance that is not simply a fixed physical constant but depends on the specific gain of the load it drives, meaning accurate delay estimation for a chain of cascaded logic gates must account for this gain-dependent Miller multiplication at each stage rather than assuming a single fixed capacitance value for every gate, a subtlety that becomes especially important in analog and mixed-signal circuit design (where amplifier stages can have substantial voltage gain) though it is a comparatively smaller effect in typical digital logic gates operating with unity or near-unity voltage swing ratios.

It is also worth noting that accurate SPICE-level circuit simulation models (such as the BSIM family of MOSFET compact models widely used in modern industrial VLSI design) represent all of these dynamic capacitance effects - gate-oxide capacitance including overlap terms, voltage-dependent junction capacitances with both bottom-wall and sidewall components, and channel-charge partitioning between source and drain - with considerably more mathematical sophistication and empirically-fitted parameters than the simplified textbook treatment given here, since accurately predicting circuit timing and power to within the tight margins required for successful first-pass silicon requires capturing second-order effects (velocity saturation, short-channel effects on capacitance, temperature dependence) well beyond the basic long-channel square-law capacitance model, though the fundamental physical origin of each capacitance component (gate-oxide, overlap, junction, channel-charge) remains exactly as described above regardless of the particular compact model's mathematical sophistication.

In summary, correctly identifying and modeling each of these parasitic capacitance sources - gate-oxide, overlap-driven Miller-amplified Cgd, and voltage-dependent junction capacitances - together with the channel-charge dynamics during switching, provides the complete picture needed for accurate timing and power analysis of any real CMOS circuit built from these devices.

This complete parasitic-capacitance and channel-charge picture is precisely what a circuit designer must understand and account for when performing transistor sizing trade-offs during physical design, since increasing a transistor's width to improve its drive strength and reduce delay simultaneously increases its own gate and junction capacitances, presenting a self-loading penalty that must be balanced against the drive-strength benefit for optimal circuit performance.

This trade-off between drive strength and self-loading is a recurring theme across nearly every transistor-sizing decision made throughout VLSI physical design.