Q17VLSI Design

Domino Logic

Domino logic is a widely used dynamic CMOS logic family specifically developed to allow multiple dynamic gates to be safely cascaded in series, addressing the fundamental problem that ordinary dynamic logic gates cannot be directly cascaded without risking incorrect evaluation, since a dynamic gate's output starts high during precharge and can only transition to low during evaluation (monotonically falling), meaning if a dynamic gate's output feeds directly into the pull-down network of a following dynamic gate, that following gate might begin discharging prematurely, before its driving input signal has actually settled to its correct final evaluated value, corrupting the result.

Domino logic solves this by adding a static CMOS inverter immediately after each dynamic gate's output, before that output feeds the next stage - during the precharge phase (clock low), the dynamic gate's internal node is precharged high by a PMOS precharge transistor, giving a static inverter output that is low; during the evaluate phase (clock high), the dynamic internal node either remains high (if the pull-down network does not conduct, output inverter stays low) or falls low (if the pull-down network does conduct based on the current inputs, output inverter output rises high) - crucially, because the internal dynamic node can only fall (never rise) during evaluation, and the inverter inverts this falling transition into a rising transition at the domino gate's actual output, each domino gate's output can only rise (never fall) during the evaluate phase, exactly like a row of falling dominoes triggering the next domino to fall in sequence (hence the name), which is precisely the monotonic, race-condition-free signal behavior needed to safely drive the pull-down network of the very next domino gate stage in a cascade.

This construction gives domino logic gates an inherently non-inverting output (since the internal dynamic AND/OR/complex-gate function is always followed by an inverting buffer stage), meaning only non-inverting logic functions (AND-OR type functions without an overall inversion) can be directly implemented in a single domino stage, requiring careful logic restructuring (using De Morgan's theorem and bubble-pushing techniques) when a design naturally calls for an inverting function, since domino logic cannot directly implement functions such as NAND or NOR without an additional inverting stage that would break the monotonic cascading property. Domino logic gates offer the same area and speed advantages as ordinary dynamic logic (smaller transistor count than static CMOS, fast switching due to lower gate capacitance) while additionally solving the direct-cascading problem, making domino logic historically popular for high-speed datapath and arithmetic circuit design (adders, multipliers) in high-performance microprocessors, though it remains susceptible to the charge-leakage and charge-sharing problems inherent to any dynamic logic family, requiring additional keeper-transistor or other charge-retention circuit techniques (examined in relation to another question in this examination) to maintain correct operation, particularly at the lower clock frequencies or larger fan-in gates where charge leakage has more time to corrupt the precharged dynamic node before evaluation completes.