Q15VLSI Design

Stick Diagrams and Component Symbols

A stick diagram is a simplified, topological (rather than precisely-dimensioned geometric) representation of a VLSI layout, used during the early physical design stage to plan the relative placement and interconnection of transistors and wiring layers before committing to detailed, exact layout geometry - a stick diagram captures the correct connectivity and relative arrangement of the various layers (polysilicon, diffusion, metal) using simple colored or patterned lines and symbols, without needing to specify precise widths, spacings, or coordinates, allowing a designer to quickly verify a proposed circuit's layout feasibility and estimate its rough area before investing the considerably greater effort required for full geometric (mask-level) layout design.

Standard stick diagram conventions use distinct colors (or line patterns, when drawn without color) to represent each physical layer: n-diffusion is conventionally shown in green, p-diffusion in brown or yellow, polysilicon (gate material) in red, and metal interconnect in blue, with a transistor formed wherever a polysilicon line crosses a diffusion line of either type (an n-diffusion crossing forms an NMOS transistor, a p-diffusion crossing forms a PMOS transistor). Contacts (connecting diffusion or polysilicon up to the metal layer) and vias (connecting between different metal layers in multi-layer-metal processes) are shown as filled circles, crosses, or squares at the specific point where two different layers need to be electrically connected, distinguishing a genuine electrical connection from a mere visual crossing of two layers that are not actually meant to connect (which pass over/under each other without any contact symbol).

Additional conventions include representing the NMOS transistors of a CMOS stick diagram in a lower horizontal band (closer to the ground rail) and the PMOS transistors in an upper horizontal band (closer to the VDD rail), with polysilicon gate lines running vertically between the two bands to connect corresponding NMOS and PMOS transistor gates driven by the same input signal, and with the n-well boundary (within which all PMOS transistors must be placed, for an n-well CMOS process) shown as a dashed boundary line enclosing the entire PMOS transistor band. This structured, banded arrangement (NMOS band, polysilicon gates crossing vertically, PMOS band, all within the constraints of the n-well boundary) is what allows the stick diagram to quickly and clearly convey the overall layout topology of a complete CMOS gate or small block, serving as the essential intermediate design step between a gate's Boolean/transistor-level schematic and its final, fully-dimensioned geometric mask layout.