Q14VLSI Design

CMOS Logic Circuit for Z=[A(B+C)+DE]

Since static CMOS logic gates are naturally inverting (a single CMOS gate stage directly realizes the complement of its pull-down network's Boolean function), the pull-down network of a single CMOS gate is designed to directly implement Z' (the complement of the target function Z), with the complementary (dual) PMOS pull-up network automatically following from De Morgan's theorem applied to the series-parallel structure of the pull-down network.

Applying De Morgan's law to Z=A(B+C)+DE: letting X=A(B+C), Z=X+DE, so Z' = X'.(DE)' = X'.(D'+E'). And X' = (A(B+C))' = A' + (B+C)' = A' + B'C'. Substituting back:

This is the Boolean function that the pull-down (NMOS) network of the single-stage CMOS gate directly implements. The pull-down network structure is read directly off this expression: the two parenthesized OR-terms (A'+B'C') and (D'+E') are connected in series with each other (representing the AND between them), and within each parenthesized term, the OR is realized as a parallel combination of the corresponding NMOS branches - specifically, an NMOS transistor gated by A' in parallel with a series combination of NMOS transistors gated by B' and C' (implementing A'+B'C'), this whole parallel-series sub-network placed in series with a second parallel combination of NMOS transistors gated by D' and E' (implementing D'+E').

The complementary PMOS pull-up network, by the standard CMOS dual-network construction rule (series becomes parallel and vice versa, with each transistor's gate signal unchanged), consists of a PMOS gated by A' in series with a parallel combination of PMOS transistors gated by B' and C', this whole sub-network in parallel with a series combination of PMOS transistors gated by D' and E'. Note that every transistor gate in this gate (both pull-up and pull-down networks) is driven by the complemented input signals A', B', C', D', E' - if only the true (uncomplemented) signals A, B, C, D, E are available as primary inputs, five separate inverters would be needed ahead of this gate to generate the required complements, or alternatively, the gate could be redesigned to directly accept and internally invert the true signals as an added first stage, a common practical consideration when implementing complex AOI/OAI gates in real CMOS designs.