Q6VLSI Design

NORA (NO RAce) CMOS is a clocked dynamic CMOS logic family specifically designed to allow multiple dynamic logic gates to be cascaded directly, one feeding the next, without the race conditions and incorrect evaluation that would occur if ordinary dynamic gates (each independently precharged and evaluated on the same clock) were cascaded naively. NORA CMOS achieves this by alternating 'n-blocks' (dynamic gates using NMOS pull-down evaluation logic) and 'p-blocks' (dynamic gates using PMOS pull-up evaluation logic) in successive stages, each block type precharging and evaluating on opposite clock phases relative to its neighbor, ensuring that by the time a given stage evaluates, its driving input from the previous stage has already stabilized to its correct, settled value rather than being mid-transition.